www.pudn.com > jaguar2s.zip > rad2_sqncr.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :1.0 |
--*|Date of Last Revision :12/23/1998 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity rad2_sqncr is
port(
reset :in std_logic;
core_clk :in std_logic;
startpc :in std_logic;
rad2go :in std_logic;
N_select :in std_logic_vector(2 downto 0);
en_rad2_exp :out std_logic;
iram_we :out std_logic;
oram_we :out std_logic;
rom_addr :out std_logic_vector(6 downto 0);
iram_addra :out std_logic_vector(7 downto 0);
iram_addrb :out std_logic_vector(7 downto 0);
oram_addra :out std_logic_vector(7 downto 0);
oram_addrb :out std_logic_vector(7 downto 0);
null_pass :out std_logic;
pass :out std_logic_vector(3 downto 0);
done :out std_logic;
direction :out std_logic
);
end rad2_sqncr;
architecture structure of rad2_sqncr is
component rad2_oram_addr_cmpt_last
port(
N_select :in std_logic_vector(2 downto 0);
oram_addra_nrm :in std_logic_vector(7 downto 0);
oram_addrb_nrm :in std_logic_vector(7 downto 0);
oram_addra_new :out std_logic_vector(7 downto 0);
oram_addrb_new :out std_logic_vector(7 downto 0)
);
end component;
component rad2_addr_cmpt
port(
N_select :in std_logic_vector(2 downto 0);
iteration :in std_logic_vector(3 downto 0);
ram_cntr :in std_logic_vector(6 downto 0);
addra :out std_logic_vector(7 downto 0);
addrb :out std_logic_vector(7 downto 0)
);
end component;
component rad2_romaddr_cmpt
port(
N_select :in std_logic_vector(2 downto 0);
iteration :in std_logic_vector(3 downto 0);
rom_cntr :in std_logic_vector(6 downto 0);
rom_addr :out std_logic_vector(6 downto 0)
);
end component;
signal TERMCNT :std_logic_vector(7 downto 0);
signal LAST_ITERATION :std_logic_vector(3 downto 0);
signal iteration :std_logic_vector(3 downto 0);
signal clk_cnt :std_logic_vector(7 downto 0);
signal rom_cntr :std_logic_vector(6 downto 0);
signal in_ram_cntr :std_logic_vector(6 downto 0);
signal out_ram_cntr :std_logic_vector(6 downto 0);
signal inaddra :std_logic_vector(7 downto 0);
signal inaddrb :std_logic_vector(7 downto 0);
signal outaddra :std_logic_vector(7 downto 0);
signal outaddrb :std_logic_vector(7 downto 0);
signal oram_addra_nrm :std_logic_vector(7 downto 0);
signal oram_addrb_nrm :std_logic_vector(7 downto 0);
signal oram_addra_lst :std_logic_vector(7 downto 0);
signal oram_addrb_lst :std_logic_vector(7 downto 0);
signal direction_reg :std_logic;
signal rad2_active :std_logic;
begin
pass <= iteration;
process(reset,core_clk)
begin
if (reset = '0') then
done <= '0';
elsif core_clk'event and core_clk = '1' then
if (clk_cnt = TERMCNT and iteration = LAST_ITERATION) then
done <= '1';
elsif (startpc = '1') then
done <= '0';
end if;
end if;
end process;
process(reset,core_clk)
begin
if (reset = '0') then
rad2_active <= '0';
elsif core_clk'event and core_clk = '1' then
if (rad2go = '1') then
rad2_active <= '1';
elsif (clk_cnt = TERMCNT and
iteration = LAST_ITERATION) then
rad2_active <= '0';
end if;
end if;
end process;
-- Need to keep the iterations at even
-- numbers so data finishes in output bank
-- last pass will be null-pass in some cases
process(N_select)
begin
case N_select is
when "000" => -- 8 point
TERMCNT <= "00000011";
LAST_ITERATION <= "0001";
when "001" => -- 16 point
TERMCNT <= "00000100";
LAST_ITERATION <= "0001";
when "010" => -- 32 point
TERMCNT <= "00000110";
LAST_ITERATION <= "0011";
when "011" => -- 64 point
TERMCNT <= "00001010";
LAST_ITERATION <= "0011";
when "100" => -- 128 point
TERMCNT <= "00010010";
LAST_ITERATION <= "0101";
when "101" => -- 256 point
TERMCNT <= "00100010";
LAST_ITERATION <= "0101";
when "110" => -- 512 point
TERMCNT <= "01000010";
LAST_ITERATION <= "0111";
when others => -- 1024 point
TERMCNT <= "10000010";
LAST_ITERATION <= "0111";
end case;
end process;
-- Block floating point hook
process(reset,core_clk)
begin
if (reset = '0') then
en_rad2_exp <= '0';
elsif core_clk'event and core_clk = '1' then
if (clk_cnt = TERMCNT and rad2_active = '1') then
en_rad2_exp <= '1';
else
en_rad2_exp <= '0';
end if;
end if;
end process;
--*****************************************************
-- Write enables
--*****************************************************
process(reset,core_clk)
begin
if (reset = '0') then
oram_we <= '0';
elsif core_clk'event and core_clk = '1' then
if (clk_cnt = "00000010" and
(iteration = "0001" or
iteration = "0011" or
iteration = "0101" or
iteration = "0111")) then
oram_we <= '1';
elsif (clk_cnt = TERMCNT) then
oram_we <= '0';
end if;
end if;
end process;
process(reset,core_clk)
begin
if (reset = '0') then
iram_we <= '0';
elsif core_clk'event and core_clk = '1' then
if (clk_cnt = "00000010" and
(iteration = "0000" or
iteration = "0010" or
iteration = "0100" or
iteration = "0110")) then
iram_we <= '1';
elsif (clk_cnt = TERMCNT) then
iram_we <= '0';
end if;
end if;
end process;
--*****************************************************
-- control the ram addresses
--*****************************************************
cmpt_last_oram_addr:rad2_oram_addr_cmpt_last
port map(
N_select => N_select,
oram_addra_nrm => oram_addra_nrm,
oram_addrb_nrm => oram_addrb_nrm,
oram_addra_new => oram_addra_lst,
oram_addrb_new => oram_addrb_lst
);
process(iteration,oram_addra_nrm,oram_addrb_nrm,
oram_addra_lst,oram_addrb_lst,LAST_ITERATION)
begin
if (iteration = LAST_ITERATION) then
oram_addra <= oram_addra_lst;
oram_addrb <= oram_addrb_lst;
else
oram_addra <= oram_addra_nrm;
oram_addrb <= oram_addrb_nrm;
end if;
end process;
process(direction_reg,inaddra,inaddrb,outaddra,outaddrb)
begin
if (direction_reg = '0') then
oram_addra_nrm <= inaddra;
oram_addrb_nrm <= inaddrb;
iram_addra <= outaddra;
iram_addrb <= outaddrb;
else
oram_addra_nrm <= outaddra;
oram_addrb_nrm <= outaddrb;
iram_addra <= inaddra;
iram_addrb <= inaddrb;
end if;
end process;
process(reset,core_clk)
begin
if (reset = '0') then
in_ram_cntr <= "0000000";
elsif core_clk'event and core_clk = '1' then
if (rad2go = '1' or clk_cnt = TERMCNT) then
in_ram_cntr <= "0000000";
elsif (rad2_active = '1') then
in_ram_cntr <= in_ram_cntr + "0000001";
end if;
end if;
end process;
cmpt_iram_addr:rad2_addr_cmpt
port map(
N_select => N_select,
iteration => iteration,
ram_cntr => in_ram_cntr,
addra => inaddra,
addrb => inaddrb
);
process(reset,core_clk)
begin
if (reset = '0') then
out_ram_cntr <= "0000000";
elsif core_clk'event and core_clk = '1' then
if (rad2go = '1' or clk_cnt = TERMCNT) then
out_ram_cntr <= "1111101";-- inaddr - 2
elsif (rad2_active = '1') then
out_ram_cntr <= out_ram_cntr + "0000001";
end if;
end if;
end process;
cmpt_oram_addr:rad2_addr_cmpt
port map(
N_select => N_select,
iteration => iteration,
ram_cntr => out_ram_cntr,
addra => outaddra,
addrb => outaddrb
);
--*****************************************************
-- generate the ROM address
--*****************************************************
process(reset,core_clk)
begin
if (reset = '0') then
rom_cntr <= "0000000";
elsif core_clk'event and core_clk = '1' then
if (rad2go = '1' or clk_cnt=TERMCNT) then
rom_cntr <= "0000000";
elsif (rad2_active = '1') then
rom_cntr <= rom_cntr + "0000001";
end if;
end if;
end process;
cmpt_rom_addr:rad2_romaddr_cmpt
port map(
N_select => N_select,
iteration => iteration,
rom_cntr => rom_cntr,
rom_addr => rom_addr
);
--*****************************************************
-- direction control,and cycle counter
--*****************************************************
process(N_select,iteration)
begin
if ((N_select = "110" and iteration = "0111") or
(N_select = "100" and iteration = "0101") or
(N_select = "010" and iteration = "0011") or
(N_select = "000" and iteration = "0001")) then
null_pass <= '1';
else
null_pass <= '0';
end if;
end process;
direction <= direction_reg;
process(reset,core_clk)
begin
if (reset = '0') then
iteration <= "0000";
direction_reg <= '0';
elsif core_clk'event and core_clk = '1' then
if (rad2go = '1') then
iteration <= "0000";
direction_reg <= '0';
elsif (clk_cnt = TERMCNT and rad2_active = '1') then
iteration <= iteration + "0001";
direction_reg <= not direction_reg;
end if;
end if;
end process;
-- count from 0 to 132(128 + overlap clocks per run)
process(reset,core_clk)
begin
if (reset = '0') then
clk_cnt <= "00000000";
elsif core_clk'event and core_clk = '1' then
if (rad2go = '1' or clk_cnt = TERMCNT) then
clk_cnt <= "00000000";
elsif (rad2_active = '1') then
clk_cnt <= clk_cnt + "00000001";
end if;
end if;
end process;
end structure;