www.pudn.com > jaguar2s.zip > rad2_oram_addr_cmpt_last.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                           :1.0                   | 
--*|Date of Last Revision             :12/23/1998            | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
 
entity rad2_oram_addr_cmpt_last is 
    port( 
        N_select           :in std_logic_vector(2 downto 0); 
        oram_addra_nrm     :in std_logic_vector(7 downto 0); 
        oram_addrb_nrm     :in std_logic_vector(7 downto 0); 
        oram_addra_new     :out std_logic_vector(7 downto 0); 
        oram_addrb_new     :out std_logic_vector(7 downto 0) 
    ); 
end rad2_oram_addr_cmpt_last; 
 
architecture structure of rad2_oram_addr_cmpt_last is 
 
    signal oram_addra_br  :std_logic_vector(7 downto 0); 
    signal oram_addrb_br  :std_logic_vector(7 downto 0); 
 
begin  
 
    oram_addra_br <= oram_addra_nrm(0) &  
                     oram_addra_nrm(1) &  
                     oram_addra_nrm(2) & 
                     oram_addra_nrm(3) & 
                     oram_addra_nrm(4) & 
                     oram_addra_nrm(5) & 
                     oram_addra_nrm(6) & 
                     oram_addra_nrm(7); 
 
    oram_addrb_br <= oram_addrb_nrm(0) &  
                     oram_addrb_nrm(1) &  
                     oram_addrb_nrm(2) & 
                     oram_addrb_nrm(3) & 
                     oram_addrb_nrm(4) & 
                     oram_addrb_nrm(5) & 
                     oram_addrb_nrm(6) & 
                     oram_addrb_nrm(7); 
 
    process(oram_addra_nrm,oram_addrb_nrm, 
            oram_addra_br,oram_addrb_br,N_select) 
    begin 
        case N_select is 
            when "000" =>  
                 oram_addra_new <= "0000000" & oram_addra_br(7); 
                 oram_addrb_new <= "0000000" & oram_addrb_br(7); 
            when "001" =>  
                 oram_addra_new <= "000000" & oram_addra_br(7 downto 6); 
                 oram_addrb_new <= "000000" & oram_addrb_br(7 downto 6); 
            when "010" =>  
                 oram_addra_new <= "00000" & oram_addra_br(7 downto 5); 
                 oram_addrb_new <= "00000" & oram_addrb_br(7 downto 5); 
            when "011" =>  
                 oram_addra_new <= "0000" & oram_addra_br(7 downto 4); 
                 oram_addrb_new <= "0000" & oram_addrb_br(7 downto 4); 
            when "100" =>  
                 oram_addra_new <= "000" & oram_addra_br(7 downto 3); 
                 oram_addrb_new <= "000" & oram_addrb_br(7 downto 3); 
            when "101" =>  
                 oram_addra_new <= "00" & oram_addra_br(7 downto 2); 
                 oram_addrb_new <= "00" & oram_addrb_br(7 downto 2); 
            when "110" =>  
                 oram_addra_new <= '0' & oram_addra_br(7 downto 1); 
                 oram_addrb_new <= '0' & oram_addrb_br(7 downto 1); 
            when others =>  
                 oram_addra_new <= oram_addra_br; 
                 oram_addrb_new <= oram_addrb_br; 
        end case; 
    end process; 
         
end structure;