www.pudn.com > jaguar2s.zip > rad2_addr_cmpt.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                           :1.0                   | 
--*|Date of Last Revision             :12/23/1998            | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all; 
 
entity rad2_addr_cmpt is 
    port( 
        N_select           :in std_logic_vector(2 downto 0); 
        iteration          :in std_logic_vector(3 downto 0); 
        ram_cntr           :in std_logic_vector(6 downto 0); 
        addra              :out std_logic_vector(7 downto 0); 
        addrb              :out std_logic_vector(7 downto 0) 
    ); 
end rad2_addr_cmpt; 
 
architecture structure of rad2_addr_cmpt is 
 
    signal new_iteration :std_logic_vector(3 downto 0); 
    signal offset        :std_logic_vector(3 downto 0); 
 
begin 
     
    process(N_select) 
    begin 
        case N_select is 
            when "000" => offset <= "0111"; 
            when "001" => offset <= "0110"; 
            when "010" => offset <= "0101"; 
            when "011" => offset <= "0100"; 
            when "100" => offset <= "0011"; 
            when "101" => offset <= "0010"; 
            when "110" => offset <= "0001"; 
            when others => offset <= "0000"; 
        end case; 
    end process; 
 
    new_iteration <= iteration + offset; 
 
    process(new_iteration,ram_cntr) 
    begin 
        case new_iteration is 
            when "0000" =>  
                addra <= '0' & ram_cntr; 
                addrb <= '1' & ram_cntr; 
            when "0001" =>  
                addra <= ram_cntr(6) & '0' &  
                         ram_cntr(5 downto 0); 
                addrb <= ram_cntr(6) & '1' &  
                         ram_cntr(5 downto 0); 
            when "0010" =>  
                addra <= ram_cntr(6 downto 5) & '0' &  
                         ram_cntr(4 downto 0); 
                addrb <= ram_cntr(6 downto 5) & '1' &  
                         ram_cntr(4 downto 0); 
            when "0011" =>  
                addra <= ram_cntr(6 downto 4) & '0' &  
                         ram_cntr(3 downto 0); 
                addrb <= ram_cntr(6 downto 4) & '1' &  
                         ram_cntr(3 downto 0); 
            when "0100" =>  
                addra <= ram_cntr(6 downto 3) & '0' &  
                         ram_cntr(2 downto 0); 
                addrb <= ram_cntr(6 downto 3) & '1' &  
                         ram_cntr(2 downto 0); 
            when "0101" =>  
                addra <= ram_cntr(6 downto 2) & '0' &  
                         ram_cntr(1 downto 0); 
                addrb <= ram_cntr(6 downto 2) & '1' &  
                         ram_cntr(1 downto 0); 
            when "0110" =>  
                addra <= ram_cntr(6 downto 1) & '0' &  
                         ram_cntr(0); 
                addrb <= ram_cntr(6 downto 1) & '1' &  
                         ram_cntr(0); 
            when others =>  
                addra <= ram_cntr(6 downto 0) & '0'; 
                addrb <= ram_cntr(6 downto 0) & '1'; 
       end case; 
    end process; 
         
end structure;