www.pudn.com > jaguar2s.zip > rad2_4_eval.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :1.0 |
--*|Date of Last Revision :12/23/1998 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
-- two cycles of latency through this block
-- three bits of attenuation through this block
entity rad2_4_eval is
generic(
WORD_WIDTH :integer := 32
);
port(
clk :in std_logic;
fwd :in std_logic;
rad4 :in std_logic;
W1_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W1_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
A :in std_logic_vector(WORD_WIDTH-1 downto 0);
B :in std_logic_vector(WORD_WIDTH-1 downto 0);
C :in std_logic_vector(WORD_WIDTH-1 downto 0);
D :in std_logic_vector(WORD_WIDTH-1 downto 0);
G0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G3 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end rad2_4_eval;
architecture rtl of rad2_4_eval is
component fft_mult
generic(
WORD_WIDTH :integer
);
port(
clk :in std_logic;
fwd :in std_logic;
sin_w :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
cos_w :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
X :in std_logic_vector(WORD_WIDTH-1 downto 0);
Y :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
component signed_addf
generic(
WIDTH :integer
);
port(
a :in std_logic_vector(WIDTH-1 downto 0);
b :in std_logic_vector(WIDTH-1 downto 0);
c :out std_logic_vector(WIDTH downto 0)
);
end component;
component signed_subf
generic(
WIDTH :integer
);
port(
a :in std_logic_vector(WIDTH-1 downto 0);
b :in std_logic_vector(WIDTH-1 downto 0);
c :out std_logic_vector(WIDTH downto 0)
);
end component;
signal b_mux :std_logic_vector(WORD_WIDTH-1 downto 0);
signal d_mux :std_logic_vector(WORD_WIDTH-1 downto 0);
signal S1 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S2 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S3 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S4 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S5 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S6 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S7 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S8 :std_logic_vector(WORD_WIDTH/2 downto 0);
signal S9 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S10 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S11 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S12 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S13 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S14 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S15 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S16 :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S9_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S10_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S11_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S12_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S13_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S14_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S15_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S16_mux :std_logic_vector(WORD_WIDTH/2+1 downto 0);
signal S11S12 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal S13S14 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal S13S14_tmp :std_logic_vector(WORD_WIDTH-1 downto 0);
signal S13S14_reg :std_logic_vector(WORD_WIDTH-1 downto 0);
signal S15S16 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal G0_tmp :std_logic_vector(WORD_WIDTH-1 downto 0);
signal G2_mux :std_logic_vector(WORD_WIDTH-1 downto 0);
signal sin_W3 :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal cos_W3 :std_logic_vector(WORD_WIDTH/2-1 downto 0);
begin
process(fwd,B,D,rad4)
begin
if (rad4 = '1' and fwd = '0') then
b_mux <= D;
d_mux <= B;
else
b_mux <= B;
d_mux <= D;
end if;
end process;
process(rad4,W3_sin_data,W3_cos_data,
W1_sin_data,W1_cos_data)
begin
if (rad4 = '1') then
sin_W3 <= W3_sin_data;
cos_W3 <= W3_cos_data;
else
sin_W3 <= W1_sin_data;
cos_W3 <= W1_cos_data;
end if;
end process;
s1_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => A(WORD_WIDTH-1 downto WORD_WIDTH/2),
b => C(WORD_WIDTH-1 downto WORD_WIDTH/2),
c => S1
);
s2_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => A(WORD_WIDTH-1 downto WORD_WIDTH/2),
b => C(WORD_WIDTH-1 downto WORD_WIDTH/2),
c => S2
);
s3_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => A(WORD_WIDTH/2-1 downto 0),
b => C(WORD_WIDTH/2-1 downto 0),
c => S3
);
s4_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => A(WORD_WIDTH/2-1 downto 0),
b => C(WORD_WIDTH/2-1 downto 0),
c => S4
);
s5_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => b_mux(WORD_WIDTH-1 downto WORD_WIDTH/2),
b => d_mux(WORD_WIDTH-1 downto WORD_WIDTH/2),
c => S5
);
s8_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => b_mux(WORD_WIDTH-1 downto WORD_WIDTH/2),
b => d_mux(WORD_WIDTH-1 downto WORD_WIDTH/2),
c => S8
);
s7_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => b_mux(WORD_WIDTH/2-1 downto 0),
b => d_mux(WORD_WIDTH/2-1 downto 0),
c => S7
);
s6_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2)
port map(
a => b_mux(WORD_WIDTH/2-1 downto 0),
b => d_mux(WORD_WIDTH/2-1 downto 0),
c => S6
);
s9_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S1,
b => S5,
c => S9
);
s10_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S3,
b => S7,
c => S10
);
s11_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S2,
b => S6,
c => S11
);
s12_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S4,
b => S8,
c => S12
);
s13_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S1,
b => S5,
c => S13
);
s14_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S3,
b => S7,
c => S14
);
s15_sub:signed_subf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S2,
b => S6,
c => S15
);
s16_add:signed_addf
generic map(WIDTH => WORD_WIDTH/2+1)
port map(
a => S4,
b => S8,
c => S16
);
process(rad4,S1,S2,S3,S4,S5,S6,S7,S8,
S9,S10,S11,S12,S13,S14,S15,S16)
begin
if (rad4 = '1') then
S9_mux <= S9;
S10_mux <= S10;
S11_mux <= S11;
S12_mux <= S12;
S13_mux <= S13;
S14_mux <= S14;
S15_mux <= S15;
S16_mux <= S16;
else
S9_mux <= S1 & '0';
S10_mux <= S3 & '0';
S11_mux <= S2 & '0';
S12_mux <= S4 & '0';
S13_mux <= S5 & '0';
S14_mux <= S7 & '0';
S15_mux <= S8 & '0';
S16_mux <= S6 & '0';
end if;
end process;
S11S12 <= S11_mux(WORD_WIDTH/2+1 downto 2) &
S12_mux(WORD_WIDTH/2+1 downto 2);
S13S14 <= S13_mux(WORD_WIDTH/2+1 downto 2) &
S14_mux(WORD_WIDTH/2+1 downto 2);
S15S16 <= S15_mux(WORD_WIDTH/2+1 downto 2) &
S16_mux(WORD_WIDTH/2+1 downto 2);
-- insert a couple cycles of delay so G vectors
-- all arrive at same time.
-- attenuate by two bits for conformity
-- Gain normalization
process
begin
wait until clk'event and clk = '1';
G0_tmp <= S9_mux(WORD_WIDTH/2+1) &
S9_mux(WORD_WIDTH/2+1 downto 3) &
S10_mux(WORD_WIDTH/2+1 ) &
S10_mux(WORD_WIDTH/2+1 downto 3);
S13S14_tmp <= S13_mux(WORD_WIDTH/2+1) &
S13_mux(WORD_WIDTH/2+1 downto 3) &
S14_mux(WORD_WIDTH/2+1 ) &
S14_mux(WORD_WIDTH/2+1 downto 3);
G0 <= G0_tmp;
S13S14_reg <= S13S14_tmp;
end process;
g1_mult:fft_mult
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => clk,
fwd => fwd,
sin_w => W1_sin_data,
cos_w => W1_cos_data,
X => S11S12,
Y => G1
);
g2_mult:fft_mult
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => clk,
fwd => fwd,
sin_w => W2_sin_data,
cos_w => W2_cos_data,
X => S13S14,
Y => G2_mux
);
process(rad4,G2_mux,S13S14_reg)
begin
if (rad4 = '1') then
G2 <= G2_mux;
else
G2 <= S13S14_reg;
end if;
end process;
g3_mult:fft_mult
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => clk,
fwd => fwd,
sin_w => sin_W3,
cos_w => cos_W3,
X => S15S16,
Y => G3
);
end rtl;