www.pudn.com > jaguar2s.zip > output_scaling.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                           :1.0                   | 
--*|Date of Last Revision             :12/23/1998            | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library ieee;  
use ieee.std_logic_1164.all;  
 
entity output_scaling is 
    generic( 
        EXP_WIDTH       :integer := 5; 
        WORD_WIDTH      :integer := 32 
    ); 
    port( 
        clk             :in std_logic; 
        startp          :in std_logic; 
        exp             :in std_logic_vector(EXP_WIDTH-1 downto 0); 
        I               :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        Q               :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        I_norm          :out std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        Q_norm          :out std_logic_vector(WORD_WIDTH/2-1 downto 0) 
    ); 
end output_scaling;  
 
architecture behavior of output_scaling is  
 
    component Lshifter 
    generic( 
        EXP_WIDTH       :integer; 
        WORD_WIDTH      :integer 
    ); 
    port(  
        shftval         :in std_logic_vector(EXP_WIDTH-1 downto 0); 
        a               :in std_logic_vector(WORD_WIDTH/2-1 downto 0);  
        b               :out std_logic_vector(WORD_WIDTH/2-1 downto 0) 
    );  
    end component;  
 
    signal out_exp      :std_logic_vector(EXP_WIDTH-1 downto 0); 
 
begin  
 
     -- latch last rad2 exponent, and hold throughout next frame 
     -- as output shift val...not the same as output exponent. 
     process 
     begin 
         wait until clk'event and clk = '1'; 
         if (startp = '1') then 
             out_exp <= exp; 
         end if; 
     end process; 
 
     I_shift:Lshifter 
     generic map(EXP_WIDTH => EXP_WIDTH, 
                 WORD_WIDTH => WORD_WIDTH) 
     port map(  
         shftval => out_exp, 
         a       => I(WORD_WIDTH/2-1 downto 0), 
         b       => I_norm(WORD_WIDTH/2-1 downto 0) 
     );  
 
     Q_shift:Lshifter 
     generic map(EXP_WIDTH => EXP_WIDTH, 
                 WORD_WIDTH => WORD_WIDTH) 
     port map(  
         shftval => out_exp, 
         a       => Q(WORD_WIDTH/2-1 downto 0), 
         b       => Q_norm(WORD_WIDTH/2-1 downto 0) 
     );  
 
end behavior;