www.pudn.com > jaguar2s.zip > output_ram_bank.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :2.0 |
--*|Date of Last Revision :02/23/2001 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity output_ram_bank is
generic(
WORD_WIDTH :integer := 32
);
port(
reset :in std_logic;
pass :in std_logic_vector(3 downto 0);
startp :in std_logic;
N_select :in std_logic_vector(2 downto 0);
--stage2 access
core_clk :in std_logic;
wea :in std_logic;
web :in std_logic;
addra :in std_logic_vector(7 downto 0);
addrb :in std_logic_vector(7 downto 0);
datatra0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafra1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafra2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafra3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
-- stage3 access
smplout_addr :in std_logic_vector(9 downto 0);
smplout_I :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplout_Q :out std_logic_vector(WORD_WIDTH/2-1 downto 0)
);
end output_ram_bank;
architecture structure of output_ram_bank is
component RAM2RW4x256xM
generic (
WORD_WIDTH :integer
);
port (
clk :in std_logic;
pass :in std_logic_vector(3 downto 0);
wea0 :in std_logic;
web0 :in std_logic;
addra0 :in std_logic_vector(7 downto 0);
addrb0 :in std_logic_vector(7 downto 0);
dataina0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
wea1 :in std_logic;
web1 :in std_logic;
addra1 :in std_logic_vector(7 downto 0);
addrb1 :in std_logic_vector(7 downto 0);
dataina1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
wea2 :in std_logic;
web2 :in std_logic;
addra2 :in std_logic_vector(7 downto 0);
addrb2 :in std_logic_vector(7 downto 0);
dataina2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
wea3 :in std_logic;
web3 :in std_logic;
addra3 :in std_logic_vector(7 downto 0);
addrb3 :in std_logic_vector(7 downto 0);
dataina3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb3 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
signal banka_wea0 :std_logic;
signal banka_web0 :std_logic;
signal banka_addra0 :std_logic_vector(7 downto 0);
signal banka_dataouta0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_wea1 :std_logic;
signal banka_web1 :std_logic;
signal banka_addra1 :std_logic_vector(7 downto 0);
signal banka_dataouta1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_wea2 :std_logic;
signal banka_web2 :std_logic;
signal banka_addra2 :std_logic_vector(7 downto 0);
signal banka_dataouta2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_wea3 :std_logic;
signal banka_web3 :std_logic;
signal banka_addra3 :std_logic_vector(7 downto 0);
signal banka_dataouta3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea0 :std_logic;
signal bankb_web0 :std_logic;
signal bankb_addra0 :std_logic_vector(7 downto 0);
signal bankb_dataouta0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea1 :std_logic;
signal bankb_web1 :std_logic;
signal bankb_addra1 :std_logic_vector(7 downto 0);
signal bankb_dataouta1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea2 :std_logic;
signal bankb_web2 :std_logic;
signal bankb_addra2 :std_logic_vector(7 downto 0);
signal bankb_dataouta2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea3 :std_logic;
signal bankb_web3 :std_logic;
signal bankb_addra3 :std_logic_vector(7 downto 0);
signal bankb_dataouta3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bank_sel :std_logic;
signal smplout_IQ :std_logic_vector(WORD_WIDTH-1 downto 0);
signal smplout_addr_br :std_logic_vector(9 downto 0);
signal zero,one :std_logic;
signal out_mux :std_logic_vector(1 downto 0);
signal pass_a :std_logic_vector(3 downto 0);
signal pass_b :std_logic_vector(3 downto 0);
begin
zero <= '0';
one <= '1';
smplout_I <= smplout_IQ(WORD_WIDTH-1 downto WORD_WIDTH/2);
smplout_Q <= smplout_IQ(WORD_WIDTH/2-1 downto 0);
-- doesn't matter what the value of bank_sel
-- is, as long as it increments on startp
process(reset,core_clk)
begin
if (reset = '0') then
bank_sel <= '0';
elsif core_clk'event and core_clk='1' then
if (startp = '1') then
bank_sel <= not bank_sel;
end if;
end if;
end process;
-- need to delay output mux by one cycle to
-- account for clock delay of addr->data
process
begin
wait until core_clk'event and core_clk='1';
out_mux <= smplout_addr_br(9 downto 8);
end process;
-- bit reverse the output address.
smplout_addr_br <= smplout_addr(1) &
smplout_addr(0) &
smplout_addr(9) &
smplout_addr(8) &
smplout_addr(7) &
smplout_addr(6) &
smplout_addr(5) &
smplout_addr(4) &
smplout_addr(3) &
smplout_addr(2);
process(bank_sel,wea,web,addra,pass,
smplout_addr_br,out_mux,
banka_dataouta0,banka_dataouta1,
banka_dataouta2,banka_dataouta3,
bankb_dataouta0,bankb_dataouta1,
bankb_dataouta2,bankb_dataouta3,
banka_dataoutb0,banka_dataoutb1,
banka_dataoutb2,banka_dataoutb3,
bankb_dataoutb0,bankb_dataoutb1,
bankb_dataoutb2,bankb_dataoutb3)
begin
if (bank_sel = '1') then
pass_a <= pass;
pass_b <= "0001";
banka_wea0 <= wea;
banka_web0 <= web;
banka_addra0 <= addra;
banka_wea1 <= wea;
banka_web1 <= web;
banka_addra1 <= addra;
banka_wea2 <= wea;
banka_web2 <= web;
banka_addra2 <= addra;
banka_wea3 <= wea;
banka_web3 <= web;
banka_addra3 <= addra;
datafra0 <= banka_dataouta0;
datafra1 <= banka_dataouta1;
datafra2 <= banka_dataouta2;
datafra3 <= banka_dataouta3;
datafrb0 <= banka_dataoutb0;
datafrb1 <= banka_dataoutb1;
datafrb2 <= banka_dataoutb2;
datafrb3 <= banka_dataoutb3;
case out_mux is
when "00" => smplout_IQ <= bankb_dataouta0;
when "01" => smplout_IQ <= bankb_dataouta1;
when "10" => smplout_IQ <= bankb_dataouta2;
when others => smplout_IQ <= bankb_dataouta3;
end case;
bankb_wea0 <= '0';
bankb_web0 <= '0';
bankb_addra0 <= smplout_addr_br(7 downto 0);
bankb_wea1 <= '0';
bankb_web1 <= '0';
bankb_addra1 <= smplout_addr_br(7 downto 0);
bankb_wea2 <= '0';
bankb_web2 <= '0';
bankb_addra2 <= smplout_addr_br(7 downto 0);
bankb_wea3 <= '0';
bankb_web3 <= '0';
bankb_addra3 <= smplout_addr_br(7 downto 0);
else
pass_b <= pass;
pass_a <= "0001";
bankb_wea0 <= wea;
bankb_web0 <= web;
bankb_addra0 <= addra;
bankb_wea1 <= wea;
bankb_web1 <= web;
bankb_addra1 <= addra;
bankb_wea2 <= wea;
bankb_web2 <= web;
bankb_addra2 <= addra;
bankb_wea3 <= wea;
bankb_web3 <= web;
bankb_addra3 <= addra;
datafra0 <= bankb_dataouta0;
datafra1 <= bankb_dataouta1;
datafra2 <= bankb_dataouta2;
datafra3 <= bankb_dataouta3;
datafrb0 <= bankb_dataoutb0;
datafrb1 <= bankb_dataoutb1;
datafrb2 <= bankb_dataoutb2;
datafrb3 <= bankb_dataoutb3;
case out_mux is
when "00" => smplout_IQ <= banka_dataouta0;
when "01" => smplout_IQ <= banka_dataouta1;
when "10" => smplout_IQ <= banka_dataouta2;
when others => smplout_IQ <= banka_dataouta3;
end case;
banka_wea0 <= '0';
banka_web0 <= '0';
banka_addra0 <= smplout_addr_br(7 downto 0);
banka_wea1 <= '0';
banka_web1 <= '0';
banka_addra1 <= smplout_addr_br(7 downto 0);
banka_wea2 <= '0';
banka_web2 <= '0';
banka_addra2 <= smplout_addr_br(7 downto 0);
banka_wea3 <= '0';
banka_web3 <= '0';
banka_addra3 <= smplout_addr_br(7 downto 0);
end if;
end process;
banka:RAM2RW4x256xM
generic map(
WORD_WIDTH => WORD_WIDTH
)
port map(
clk => core_clk,
pass => pass_a,
wea0 => banka_wea0,
web0 => banka_web0,
addra0 => banka_addra0,
addrb0 => addrb,
dataina0 => datatra0,
datainb0 => datatrb0,
dataouta0 => banka_dataouta0,
dataoutb0 => banka_dataoutb0,
wea1 => banka_wea1,
web1 => banka_web1,
addra1 => banka_addra1,
addrb1 => addrb,
dataina1 => datatra1,
datainb1 => datatrb1,
dataouta1 => banka_dataouta1,
dataoutb1 => banka_dataoutb1,
wea2 => banka_wea2,
web2 => banka_web2,
addra2 => banka_addra2,
addrb2 => addrb,
dataina2 => datatra2,
datainb2 => datatrb2,
dataouta2 => banka_dataouta2,
dataoutb2 => banka_dataoutb2,
wea3 => banka_wea3,
web3 => banka_web3,
addra3 => banka_addra3,
addrb3 => addrb,
dataina3 => datatra3,
datainb3 => datatrb3,
dataouta3 => banka_dataouta3,
dataoutb3 => banka_dataoutb3
);
bankb:RAM2RW4x256xM
generic map(
WORD_WIDTH => WORD_WIDTH
)
port map(
clk => core_clk,
pass => pass_b,
wea0 => bankb_wea0,
web0 => bankb_web0,
addra0 => bankb_addra0,
addrb0 => addrb,
dataina0 => datatra0,
datainb0 => datatrb0,
dataouta0 => bankb_dataouta0,
dataoutb0 => bankb_dataoutb0,
wea1 => bankb_wea1,
web1 => bankb_web1,
addra1 => bankb_addra1,
addrb1 => addrb,
dataina1 => datatra1,
datainb1 => datatrb1,
dataouta1 => bankb_dataouta1,
dataoutb1 => bankb_dataoutb1,
wea2 => bankb_wea2,
web2 => bankb_web2,
addra2 => bankb_addra2,
addrb2 => addrb,
dataina2 => datatra2,
datainb2 => datatrb2,
dataouta2 => bankb_dataouta2,
dataoutb2 => bankb_dataoutb2,
wea3 => bankb_wea3,
web3 => bankb_web3,
addra3 => bankb_addra3,
addrb3 => addrb,
dataina3 => datatra3,
datainb3 => datatrb3,
dataouta3 => bankb_dataouta3,
dataoutb3 => bankb_dataoutb3
);
end structure;