www.pudn.com > jaguar2s.zip > jaguar2_io.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                               :2.0               | 
--*|Date of Last Revision                 :02/23/2001        | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
 
entity jaguar2_io is 
    generic( 
        EXP_WIDTH        :integer := 5; 
        WORD_WIDTH       :integer := 32 
    ); 
    port( 
        core_clk_pin     :in std_logic; 
        reset_pin        :in std_logic; 
        startp_pin       :in std_logic; 
        fwd_pin          :in std_logic; 
        N_select_pin     :in std_logic_vector(2 downto 0); 
        smplin_we_pin    :in std_logic; 
        smplin_addr_pin  :in std_logic_vector(9 downto 0); 
        smplin_I_pin     :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplin_Q_pin     :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplout_addr_pin :in std_logic_vector(9 downto 0); 
        smplout_I_pin    :out std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplout_Q_pin    :out std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        done_pin         :out std_logic; 
        pow_exp_pin      :out std_logic_vector(EXP_WIDTH downto 0) 
    ); 
end jaguar2_io; 
 
architecture behavior of jaguar2_io is 
 
    component jaguar2_core 
    generic( 
        EXP_WIDTH        :integer; 
        WORD_WIDTH       :integer 
    ); 
    port( 
        core_clk         :in std_logic; 
        reset            :in std_logic; 
        startp           :in std_logic; 
        fwd              :in std_logic; 
        N_select         :in std_logic_vector(2 downto 0); 
        smplin_we        :in std_logic; 
        smplin_addr      :in std_logic_vector(9 downto 0); 
        smplin_I         :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplin_Q         :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplout_addr     :in std_logic_vector(9 downto 0); 
        smplout_I        :out std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplout_Q        :out std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        done             :out std_logic; 
        pow_exp          :out std_logic_vector(EXP_WIDTH downto 0) 
    ); 
    end component; 
 
    signal core_clk      :std_logic; 
    signal reset         :std_logic; 
    signal startp        :std_logic; 
    signal fwd           :std_logic; 
    signal N_select	 :std_logic_vector(2 downto 0); 
    signal smplin_we     :std_logic; 
    signal smplin_addr   :std_logic_vector(9 downto 0); 
    signal smplin_I      :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
    signal smplin_Q      :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
    signal smplout_addr  :std_logic_vector(9 downto 0); 
    signal smplout_I     :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
    signal smplout_Q     :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
    signal done          :std_logic; 
    signal pow_exp       :std_logic_vector(EXP_WIDTH downto 0); 
 
begin  
 
    -- Add technology I/O cells here 
    core_clk <= core_clk_pin; 
    reset <= reset_pin; 
    startp <= startp_pin; 
    fwd <= fwd_pin; 
    N_select <= N_select_pin; 
    smplin_we <= smplin_we_pin; 
    smplin_addr <= smplin_addr_pin; 
    smplin_I <= smplin_I_pin; 
    smplin_Q <= smplin_Q_pin; 
    smplout_addr <= smplout_addr_pin; 
    smplout_I_pin <= smplout_I; 
    smplout_Q_pin <= smplout_Q; 
    done_pin <= done; 
    pow_exp_pin <= pow_exp; 
        
    core:jaguar2_core 
    generic map(EXP_WIDTH => EXP_WIDTH, 
                WORD_WIDTH => WORD_WIDTH) 
    port map( 
        core_clk => core_clk, 
        reset => reset, 
        startp => startp, 
        fwd => fwd, 
        N_select => N_select, 
        smplin_we => smplin_we, 
        smplin_addr => smplin_addr, 
        smplin_I => smplin_I, 
        smplin_Q => smplin_Q, 
        smplout_addr => smplout_addr, 
        smplout_I => smplout_I, 
        smplout_Q => smplout_Q, 
        done => done, 
        pow_exp => pow_exp 
    );  
       
end behavior;