www.pudn.com > jaguar2s.zip > jaguar2.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :2.0 |
--*|Date of Last Revision :02/23/2001 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity jaguar2_core is
generic(
EXP_WIDTH :integer := 5;
WORD_WIDTH :integer := 32
);
port(
core_clk :in std_logic;
reset :in std_logic;
startp :in std_logic;
fwd :in std_logic;
N_select :in std_logic_vector(2 downto 0);
smplin_we :in std_logic;
smplin_addr :in std_logic_vector(9 downto 0);
smplin_I :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplin_Q :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplout_addr :in std_logic_vector(9 downto 0);
smplout_I :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplout_Q :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
done :out std_logic;
pow_exp :out std_logic_vector(EXP_WIDTH downto 0)
);
end jaguar2_core;
architecture behavior of jaguar2_core is
component sequencer
port(
reset :in std_logic;
startp :in std_logic;
core_clk :in std_logic;
N_select :in std_logic_vector(2 downto 0);
null_pass :out std_logic;
iram_weab :out std_logic;
iram_addra :out std_logic_vector(7 downto 0);
iram_addrb :out std_logic_vector(7 downto 0);
oram_wea :out std_logic;
oram_web :out std_logic;
oram_addra :out std_logic_vector(7 downto 0);
oram_addrb :out std_logic_vector(7 downto 0);
rom_addr :out std_logic_vector(7 downto 0);
direction :out std_logic;
pass :out std_logic_vector(3 downto 0);
rad4 :out std_logic;
en_inp_exp :out std_logic;
done :out std_logic;
en_exp :out std_logic
);
end component;
component compute_input_exp
generic(
EXP_WIDTH :integer;
WORD_WIDTH :integer
);
port(
reset :in std_logic;
clk :in std_logic;
startp :in std_logic;
smplin_we :in std_logic;
smplin_I :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplin_Q :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
shift_val :out std_logic_vector(EXP_WIDTH-1 downto 0)
);
end component;
component input_ram_bank
generic(
WORD_WIDTH :integer
);
port(
reset :in std_logic;
pass :in std_logic_vector(3 downto 0);
N_select :in std_logic_vector(2 downto 0);
--stage1 access
startp :in std_logic;
smplin_we :in std_logic;
smplin_addr :in std_logic_vector(9 downto 0);
smplin_I :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplin_Q :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
--butterfly access
core_clk :in std_logic;
we_ab :in std_logic;
addra :in std_logic_vector(7 downto 0);
addrb :in std_logic_vector(7 downto 0);
datatra0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb3 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
component SINCOS_ROM
generic(WORD_WIDTH :integer);
port(
clk :in std_logic;
addr :in std_logic_vector(7 downto 0);
rad4 :in std_logic;
W1_sin_data :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
W1_cos_data :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_sin_data :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_cos_data :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_sin_data :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_cos_data :out std_logic_vector(WORD_WIDTH/2-1 downto 0)
);
end component;
component radix2_4
generic(
WORD_WIDTH :integer
);
port(
clk :in std_logic;
fwd :in std_logic;
null_pass :in std_logic;
rad4 :in std_logic;
W1_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W1_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W2_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_sin_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
W3_cos_data :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
datafra0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb1 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
component radix2
generic(
WORD_WIDTH :integer
);
port(
clk :in std_logic;
fwd :in std_logic;
null_pass :in std_logic;
sin_w :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
cos_w :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
X0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
X1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
G0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
G1 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
component scaling
generic(
EXP_WIDTH :integer;
WORD_WIDTH :integer
);
port(
exp :in std_logic_vector(EXP_WIDTH-1 downto 0);
data0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data0_norm :out std_logic_vector(WORD_WIDTH-1 downto 0);
data1_norm :out std_logic_vector(WORD_WIDTH-1 downto 0);
data2_norm :out std_logic_vector(WORD_WIDTH-1 downto 0);
data3_norm :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
component compute_exp
generic(
EXP_WIDTH :integer;
WORD_WIDTH :integer
);
port(
reset :in std_logic;
null_pass :in std_logic;
core_clk :in std_logic;
en_exp :in std_logic;
we :in std_logic;
data0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
exp :out std_logic_vector(EXP_WIDTH-1 downto 0)
);
end component;
component compute_pow
generic(
EXP_WIDTH :integer
);
port(
reset :in std_logic;
fwd :in std_logic;
N_select :in std_logic_vector(2 downto 0);
core_clk :in std_logic;
startp :in std_logic;
en_inp_exp :in std_logic;
en_rad_exp :in std_logic;
input_exp :in std_logic_vector(EXP_WIDTH-1 downto 0);
rad_exp :in std_logic_vector(EXP_WIDTH-1 downto 0);
pow_exp :out std_logic_vector(EXP_WIDTH downto 0)
);
end component;
component output_ram_bank
generic(
WORD_WIDTH :integer := 32
);
port(
reset :in std_logic;
pass :in std_logic_vector(3 downto 0);
N_select :in std_logic_vector(2 downto 0);
startp :in std_logic;
core_clk :in std_logic;
wea :in std_logic;
web :in std_logic;
addra :in std_logic_vector(7 downto 0);
addrb :in std_logic_vector(7 downto 0);
datatra0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatra3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafra1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafra2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafra3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
smplout_addr :in std_logic_vector(9 downto 0);
smplout_I :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplout_Q :out std_logic_vector(WORD_WIDTH/2-1 downto 0)
);
end component;
component output_scaling
generic(
EXP_WIDTH :integer;
WORD_WIDTH :integer
);
port(
clk :in std_logic;
startp :in std_logic;
exp :in std_logic_vector(EXP_WIDTH-1 downto 0);
I :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
Q :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
I_norm :out std_logic_vector(WORD_WIDTH/2-1 downto 0);
Q_norm :out std_logic_vector(WORD_WIDTH/2-1 downto 0)
);
end component;
signal N_select_reg :std_logic_vector(2 downto 0);
signal N_select_in :std_logic_vector(2 downto 0);
signal N_select_core :std_logic_vector(2 downto 0);
signal N_select_out :std_logic_vector(2 downto 0);
signal null_pass :std_logic;
signal rad4 :std_logic;
signal direction :std_logic;
signal en_exp :std_logic;
signal en_inp_exp :std_logic;
signal input_exp :std_logic_vector(EXP_WIDTH-1 downto 0);
signal rad_exp :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp :std_logic_vector(EXP_WIDTH-1 downto 0);
signal rom_addr :std_logic_vector(7 downto 0);
signal pass :std_logic_vector(3 downto 0);
signal we_exp :std_logic;
signal iram_weab :std_logic;
signal oram_wea :std_logic;
signal oram_web :std_logic;
signal W1_sin_data :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal W1_cos_data :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal W2_sin_data :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal W2_cos_data :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal W3_sin_data :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal W3_cos_data :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal datatra0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra2_rad2_4 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra3_rad2_4 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra2_rad2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatra3_rad2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatrb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatrb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatrb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datatrb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra0_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra1_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra2_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafra3_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb0_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb1_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb2_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal datafrb3_norm :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_addra :std_logic_vector(7 downto 0);
signal iram_addrb :std_logic_vector(7 downto 0);
signal iram_datafra0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafrb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafra1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafrb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafra2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafrb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafra3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal iram_datafrb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_addra :std_logic_vector(7 downto 0);
signal oram_addrb :std_logic_vector(7 downto 0);
signal oram_datafra0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafrb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafra1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafrb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafra2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafrb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafra3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal oram_datafrb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal unscaled_smplout_I :std_logic_vector(WORD_WIDTH/2-1 downto 0);
signal unscaled_smplout_Q :std_logic_vector(WORD_WIDTH/2-1 downto 0);
begin
process(reset,core_clk)
begin
if (reset = '0') then
N_select_in <= "000";
N_select_core <= "000";
N_select_out <= "000";
elsif core_clk'event and core_clk = '1' then
N_select_reg <= N_select;
if (startp = '1') then
N_select_in <= N_select_reg;
N_select_core <= N_select_in;
N_select_out <= N_select_core;
end if;
end if;
end process;
main_sqncr:sequencer
port map(
reset => reset,
startp => startp,
core_clk => core_clk,
N_select => N_select_core,
null_pass => null_pass,
iram_weab => iram_weab,
iram_addra => iram_addra,
iram_addrb => iram_addrb,
oram_wea => oram_wea,
oram_web => oram_web,
oram_addra => oram_addra,
oram_addrb => oram_addrb,
rom_addr => rom_addr,
direction => direction,
pass => pass,
rad4 => rad4,
en_inp_exp => en_inp_exp,
done => done,
en_exp => en_exp
);
inp_exp:compute_input_exp
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
reset => reset,
clk => core_clk,
startp => startp,
smplin_we => smplin_we,
smplin_I => smplin_I,
smplin_Q => smplin_Q,
shift_val => input_exp
);
input_ram:input_ram_bank
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
reset => reset,
pass => pass,
N_select => N_select_in,
smplin_we => smplin_we,
startp => startp,
smplin_addr => smplin_addr,
smplin_I => smplin_I,
smplin_Q => smplin_Q,
core_clk => core_clk,
we_ab => iram_weab,
addra => iram_addra,
addrb => iram_addrb,
datatra0 => datatra0,
datatrb0 => datatrb0,
datafra0 => iram_datafra0,
datafrb0 => iram_datafrb0,
datatra1 => datatra1,
datatrb1 => datatrb1,
datafra1 => iram_datafra1,
datafrb1 => iram_datafrb1,
datatra2 => datatra2,
datatrb2 => datatrb2,
datafra2 => iram_datafra2,
datafrb2 => iram_datafrb2,
datatra3 => datatra3,
datatrb3 => datatrb3,
datafra3 => iram_datafra3,
datafrb3 => iram_datafrb3
);
process(rad4,rad_exp,input_exp)
begin
if (rad4 = '1') then
exp <= input_exp;
else
exp <= rad_exp;
end if;
end process;
a_scaling:scaling
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
exp => exp,
data0 => datafra0,
data1 => datafra1,
data2 => datafra2,
data3 => datafra3,
data0_norm => datafra0_norm,
data1_norm => datafra1_norm,
data2_norm => datafra2_norm,
data3_norm => datafra3_norm
);
b_scaling:scaling
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
exp => exp,
data0 => datafrb0,
data1 => datafrb1,
data2 => datafrb2,
data3 => datafrb3,
data0_norm => datafrb0_norm,
data1_norm => datafrb1_norm,
data2_norm => datafrb2_norm,
data3_norm => datafrb3_norm
);
process(direction,
iram_datafra0,iram_datafra1,iram_datafra2,iram_datafra3,
iram_datafrb0,iram_datafrb1,iram_datafrb2,iram_datafrb3,
oram_datafra0,oram_datafra1,oram_datafra2,oram_datafra3,
oram_datafrb0,oram_datafrb1,oram_datafrb2,oram_datafrb3)
begin
if (direction = '1') then
datafra0 <= iram_datafra0;
datafra1 <= iram_datafra1;
datafra2 <= iram_datafra2;
datafra3 <= iram_datafra3;
datafrb0 <= iram_datafrb0;
datafrb1 <= iram_datafrb1;
datafrb2 <= iram_datafrb2;
datafrb3 <= iram_datafrb3;
else
datafra0 <= oram_datafra0;
datafra1 <= oram_datafra1;
datafra2 <= oram_datafra2;
datafra3 <= oram_datafra3;
datafrb0 <= oram_datafrb0;
datafrb1 <= oram_datafrb1;
datafrb2 <= oram_datafrb2;
datafrb3 <= oram_datafrb3;
end if;
end process;
rom:SINCOS_ROM
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => core_clk,
addr => rom_addr,
rad4 => rad4, -- rad4/rad2 switch
W1_sin_data => W1_sin_data,
W1_cos_data => W1_cos_data,
W2_sin_data => W2_sin_data,
W2_cos_data => W2_cos_data,
W3_sin_data => W3_sin_data,
W3_cos_data => W3_cos_data
);
rad2_4_stage:radix2_4
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => core_clk,
fwd => fwd,
null_pass => null_pass,
rad4 => rad4, -- rad4/rad2 switch
W1_sin_data => W1_sin_data,
W1_cos_data => W1_cos_data,
W2_sin_data => W2_sin_data,
W2_cos_data => W2_cos_data,
W3_sin_data => W3_sin_data,
W3_cos_data => W3_cos_data,
datafra0 => datafra0_norm,
datafra1 => datafra1_norm,
datafra2 => datafra2_norm,
datafra3 => datafra3_norm,
datafrb0 => datafrb0_norm,
datafrb1 => datafrb1_norm,
datatra0 => datatra0,
datatra1 => datatra1,
datatra2 => datatra2_rad2_4,
datatra3 => datatra3_rad2_4,
datatrb0 => datatrb0,
datatrb1 => datatrb1
);
rad2_stage2:radix2
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => core_clk,
fwd => fwd,
null_pass => null_pass,
sin_w => W1_sin_data,
cos_w => W1_cos_data,
X0 => datafra2_norm,
X1 => datafrb2_norm,
G0 => datatra2_rad2,
G1 => datatrb2
);
rad2_stage3:radix2
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
clk => core_clk,
fwd => fwd,
null_pass => null_pass,
sin_w => W1_sin_data,
cos_w => W1_cos_data,
X0 => datafra3_norm,
X1 => datafrb3_norm,
G0 => datatra3_rad2,
G1 => datatrb3
);
process(rad4,
datatra2_rad2_4,datatra3_rad2_4,
datatra2_rad2,datatra3_rad2)
begin
if (rad4 = '1') then
datatra2 <= datatra2_rad2_4;
datatra3 <= datatra3_rad2_4;
else
datatra2 <= datatra2_rad2;
datatra3 <= datatra3_rad2;
end if;
end process;
we_exp <= iram_weab or oram_wea or oram_web;
cmpt_exp:compute_exp
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
reset => reset,
core_clk => core_clk,
null_pass => null_pass,
en_exp => en_exp,
we => we_exp,
data0 => datatra0,
data1 => datatra1,
data2 => datatra2,
data3 => datatra3,
datb0 => datatrb0,
datb1 => datatrb1,
datb2 => datatrb2,
datb3 => datatrb3,
exp => rad_exp
);
output_ram:output_ram_bank
generic map(WORD_WIDTH => WORD_WIDTH)
port map(
reset => reset,
pass => pass,
N_select => N_select_out,
core_clk => core_clk,
startp => startp,
wea => oram_wea,
web => oram_web,
addra => oram_addra,
addrb => oram_addrb,
datatra0 => datatra0,
datatrb0 => datatrb0,
datatra1 => datatra1,
datatrb1 => datatrb1,
datatra2 => datatra2,
datatrb2 => datatrb2,
datatra3 => datatra3,
datatrb3 => datatrb3,
datafra0 => oram_datafra0,
datafrb0 => oram_datafrb0,
datafra1 => oram_datafra1,
datafrb1 => oram_datafrb1,
datafra2 => oram_datafra2,
datafrb2 => oram_datafrb2,
datafra3 => oram_datafra3,
datafrb3 => oram_datafrb3,
smplout_addr => smplout_addr,
smplout_I => unscaled_smplout_I,
smplout_Q => unscaled_smplout_Q
);
power_exp:compute_pow
generic map(EXP_WIDTH => EXP_WIDTH)
port map(
reset => reset,
fwd => fwd,
N_select => N_select_core,
core_clk => core_clk,
startp => startp,
en_inp_exp => en_inp_exp,
en_rad_exp => en_exp,
input_exp => input_exp,
rad_exp => rad_exp,
pow_exp => pow_exp
);
out_scaling:output_scaling
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
clk => core_clk,
startp => startp,
exp => rad_exp,
I => unscaled_smplout_I,
Q => unscaled_smplout_Q,
I_norm => smplout_I,
Q_norm => smplout_Q
);
end behavior;