www.pudn.com > jaguar2s.zip > input_ram_bank.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :2.0 |
--*|Date of Last Revision :02/23/2001 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
entity input_ram_bank is
generic (
WORD_WIDTH :integer := 32
);
port (
reset :in std_logic;
pass :in std_logic_vector(3 downto 0);
N_select :in std_logic_vector(2 downto 0);
--stage1 access
startp :in std_logic;
smplin_we :in std_logic;
smplin_addr :in std_logic_vector(9 downto 0);
smplin_I :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
smplin_Q :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
--butterfly access
core_clk :in std_logic;
we_ab :in std_logic;
addra :in std_logic_vector(7 downto 0);
addrb :in std_logic_vector(7 downto 0);
datatra0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datatra3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datatrb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datafra3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
datafrb3 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end input_ram_bank;
architecture structure of input_ram_bank is
component RAM2RW4x256xM
generic(
WORD_WIDTH :integer
);
port(
clk :in std_logic;
pass :in std_logic_vector(3 downto 0);
wea0 :in std_logic;
web0 :in std_logic;
addra0 :in std_logic_vector(7 downto 0);
addrb0 :in std_logic_vector(7 downto 0);
dataina0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb0 :out std_logic_vector(WORD_WIDTH-1 downto 0);
wea1 :in std_logic;
web1 :in std_logic;
addra1 :in std_logic_vector(7 downto 0);
addrb1 :in std_logic_vector(7 downto 0);
dataina1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb1 :out std_logic_vector(WORD_WIDTH-1 downto 0);
wea2 :in std_logic;
web2 :in std_logic;
addra2 :in std_logic_vector(7 downto 0);
addrb2 :in std_logic_vector(7 downto 0);
dataina2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb2 :out std_logic_vector(WORD_WIDTH-1 downto 0);
wea3 :in std_logic;
web3 :in std_logic;
addra3 :in std_logic_vector(7 downto 0);
addrb3 :in std_logic_vector(7 downto 0);
dataina3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datainb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
dataouta3 :out std_logic_vector(WORD_WIDTH-1 downto 0);
dataoutb3 :out std_logic_vector(WORD_WIDTH-1 downto 0)
);
end component;
signal banka_wea0 :std_logic;
signal banka_web0 :std_logic;
signal banka_addra0 :std_logic_vector(7 downto 0);
signal banka_dataina0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataouta0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_wea1 :std_logic;
signal banka_web1 :std_logic;
signal banka_addra1 :std_logic_vector(7 downto 0);
signal banka_dataina1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataouta1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_wea2 :std_logic;
signal banka_web2 :std_logic;
signal banka_addra2 :std_logic_vector(7 downto 0);
signal banka_dataina2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataouta2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_wea3 :std_logic;
signal banka_web3 :std_logic;
signal banka_addra3 :std_logic_vector(7 downto 0);
signal banka_dataina3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataouta3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal banka_dataoutb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea0 :std_logic;
signal bankb_web0 :std_logic;
signal bankb_addra0 :std_logic_vector(7 downto 0);
signal bankb_dataina0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataouta0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb0 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea1 :std_logic;
signal bankb_web1 :std_logic;
signal bankb_addra1 :std_logic_vector(7 downto 0);
signal bankb_dataina1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataouta1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb1 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea2 :std_logic;
signal bankb_web2 :std_logic;
signal bankb_addra2 :std_logic_vector(7 downto 0);
signal bankb_dataina2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataouta2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb2 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_wea3 :std_logic;
signal bankb_web3 :std_logic;
signal bankb_addra3 :std_logic_vector(7 downto 0);
signal bankb_dataina3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataouta3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bankb_dataoutb3 :std_logic_vector(WORD_WIDTH-1 downto 0);
signal bank_sel :std_logic;
signal smplin_IQ :std_logic_vector(WORD_WIDTH-1 downto 0);
signal smplin_addr_sel :std_logic_vector(9 downto 0);
signal one :std_logic;
begin
one <= '1';
smplin_IQ <= smplin_I & smplin_Q;
-- doesn't matter what the value of bank_sel
-- is, as long as it increments on startp
process(reset,core_clk)
begin
if (reset = '0') then
bank_sel <= '0';
elsif core_clk'event and core_clk='1' then
if (startp = '1') then
bank_sel <= not bank_sel;
end if;
end if;
end process;
process(N_select,smplin_addr)
begin
case N_select is
when "000" => --8point
smplin_addr_sel <= smplin_addr(2 downto 1) & "0000000" &
smplin_addr(0);
when "001" => --16point
smplin_addr_sel <= smplin_addr(3 downto 2) & "000000" &
smplin_addr(1 downto 0);
when "010" => --32point
smplin_addr_sel <= smplin_addr(4 downto 3) & "00000" &
smplin_addr(2 downto 0);
when "011" => --64point
smplin_addr_sel <= smplin_addr(5 downto 4) & "0000" &
smplin_addr(3 downto 0);
when "100" => --128point
smplin_addr_sel <= smplin_addr(6 downto 5) & "000" &
smplin_addr(4 downto 0);
when "101" => --256 point
smplin_addr_sel <= smplin_addr(7 downto 6) & "00" &
smplin_addr(5 downto 0);
when "110" => --512 point
smplin_addr_sel <= smplin_addr(8 downto 7) & '0' &
smplin_addr(6 downto 0);
when others => --1024 point
smplin_addr_sel <= smplin_addr;
end case;
end process;
process(bank_sel,
smplin_we,smplin_addr_sel,smplin_IQ,
addra,we_ab,
banka_dataouta0,bankb_dataouta0,
banka_dataouta1,bankb_dataouta1,
banka_dataouta2,bankb_dataouta2,
banka_dataouta3,bankb_dataouta3,
banka_dataoutb0,bankb_dataoutb0,
banka_dataoutb1,bankb_dataoutb1,
banka_dataoutb2,bankb_dataoutb2,
banka_dataoutb3,bankb_dataoutb3,
datatra0,datatra1,datatra2,datatra3)
begin
if (bank_sel='1') then
banka_wea0 <= '0';
banka_wea1 <= '0';
banka_wea2 <= '0';
banka_wea3 <= '0';
case smplin_addr_sel(9 downto 8) is
when "00" =>
banka_wea0 <= smplin_we;
when "01" =>
banka_wea1 <= smplin_we;
when "10" =>
banka_wea2 <= smplin_we;
when others =>
banka_wea3 <= smplin_we;
end case;
banka_web0 <= '0';
banka_web1 <= '0';
banka_web2 <= '0';
banka_web3 <= '0';
banka_addra0 <= smplin_addr_sel(7 downto 0);
banka_dataina0 <= smplin_IQ;
banka_addra1 <= smplin_addr_sel(7 downto 0);
banka_dataina1 <= smplin_IQ;
banka_addra2 <= smplin_addr_sel(7 downto 0);
banka_dataina2 <= smplin_IQ;
banka_addra3 <= smplin_addr_sel(7 downto 0);
banka_dataina3 <= smplin_IQ;
bankb_wea0 <= we_ab;
bankb_web0 <= we_ab;
bankb_addra0 <= addra;
bankb_dataina0 <= datatra0;
datafra0 <= bankb_dataouta0;
datafrb0 <= bankb_dataoutb0;
bankb_wea1 <= we_ab;
bankb_web1 <= we_ab;
bankb_addra1 <= addra;
bankb_dataina1 <= datatra1;
datafra1 <= bankb_dataouta1;
datafrb1 <= bankb_dataoutb1;
bankb_wea2 <= we_ab;
bankb_web2 <= we_ab;
bankb_addra2 <= addra;
bankb_dataina2 <= datatra2;
datafra2 <= bankb_dataouta2;
datafrb2 <= bankb_dataoutb2;
bankb_wea3 <= we_ab;
bankb_web3 <= we_ab;
bankb_addra3 <= addra;
bankb_dataina3 <= datatra3;
datafra3 <= bankb_dataouta3;
datafrb3 <= bankb_dataoutb3;
else -- Other Bank
bankb_wea0 <= '0';
bankb_wea1 <= '0';
bankb_wea2 <= '0';
bankb_wea3 <= '0';
case smplin_addr_sel(9 downto 8) is
when "00" =>
bankb_wea0 <= smplin_we;
when "01" =>
bankb_wea1 <= smplin_we;
when "10" =>
bankb_wea2 <= smplin_we;
when others =>
bankb_wea3 <= smplin_we;
end case;
bankb_web0 <= '0';
bankb_web1 <= '0';
bankb_web2 <= '0';
bankb_web3 <= '0';
bankb_addra0 <= smplin_addr_sel(7 downto 0);
bankb_dataina0 <= smplin_IQ;
bankb_addra1 <= smplin_addr_sel(7 downto 0);
bankb_dataina1 <= smplin_IQ;
bankb_addra2 <= smplin_addr_sel(7 downto 0);
bankb_dataina2 <= smplin_IQ;
bankb_addra3 <= smplin_addr_sel(7 downto 0);
bankb_dataina3 <= smplin_IQ;
banka_wea0 <= we_ab;
banka_web0 <= we_ab;
banka_addra0 <= addra;
banka_dataina0 <= datatra0;
datafra0 <= banka_dataouta0;
datafrb0 <= banka_dataoutb0;
banka_wea1 <= we_ab;
banka_web1 <= we_ab;
banka_addra1 <= addra;
banka_dataina1 <= datatra1;
datafra1 <= banka_dataouta1;
datafrb1 <= banka_dataoutb1;
banka_wea2 <= we_ab;
banka_web2 <= we_ab;
banka_addra2 <= addra;
banka_dataina2 <= datatra2;
datafra2 <= banka_dataouta2;
datafrb2 <= banka_dataoutb2;
banka_wea3 <= we_ab;
banka_web3 <= we_ab;
banka_addra3 <= addra;
banka_dataina3 <= datatra3;
datafra3 <= banka_dataouta3;
datafrb3 <= banka_dataoutb3;
end if;
end process;
banka:RAM2RW4x256xM
generic map(
WORD_WIDTH => WORD_WIDTH
)
port map(
clk => core_clk,
pass => pass,
wea0 => banka_wea0,
web0 => banka_web0,
addra0 => banka_addra0,
addrb0 => addrb,
dataina0 => banka_dataina0,
datainb0 => datatrb0,
dataouta0 => banka_dataouta0,
dataoutb0 => banka_dataoutb0,
wea1 => banka_wea1,
web1 => banka_web1,
addra1 => banka_addra1,
addrb1 => addrb,
dataina1 => banka_dataina1,
datainb1 => datatrb1,
dataouta1 => banka_dataouta1,
dataoutb1 => banka_dataoutb1,
wea2 => banka_wea2,
web2 => banka_web2,
addra2 => banka_addra2,
addrb2 => addrb,
dataina2 => banka_dataina2,
datainb2 => datatrb2,
dataouta2 => banka_dataouta2,
dataoutb2 => banka_dataoutb2,
wea3 => banka_wea3,
web3 => banka_web3,
addra3 => banka_addra3,
addrb3 => addrb,
dataina3 => banka_dataina3,
datainb3 => datatrb3,
dataouta3 => banka_dataouta3,
dataoutb3 => banka_dataoutb3
);
bankb:RAM2RW4x256xM
generic map(
WORD_WIDTH => WORD_WIDTH
)
port map(
clk => core_clk,
pass => pass,
wea0 => bankb_wea0,
web0 => bankb_web0,
addra0 => bankb_addra0,
addrb0 => addrb,
dataina0 => bankb_dataina0,
datainb0 => datatrb0,
dataouta0 => bankb_dataouta0,
dataoutb0 => bankb_dataoutb0,
wea1 => bankb_wea1,
web1 => bankb_web1,
addra1 => bankb_addra1,
addrb1 => addrb,
dataina1 => bankb_dataina1,
datainb1 => datatrb1,
dataouta1 => bankb_dataouta1,
dataoutb1 => bankb_dataoutb1,
wea2 => bankb_wea2,
web2 => bankb_web2,
addra2 => bankb_addra2,
addrb2 => addrb,
dataina2 => bankb_dataina2,
datainb2 => datatrb2,
dataouta2 => bankb_dataouta2,
dataoutb2 => bankb_dataoutb2,
wea3 => bankb_wea3,
web3 => bankb_web3,
addra3 => bankb_addra3,
addrb3 => addrb,
dataina3 => bankb_dataina3,
datainb3 => datatrb3,
dataouta3 => bankb_dataouta3,
dataoutb3 => bankb_dataoutb3
);
end structure;