www.pudn.com > jaguar2s.zip > gen_exp_IQ.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                               :1.0               | 
--*|Date of Last Revision                 :12/23/1998        | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
 
entity gen_exp_IQ is 
   generic( 
       EXP_WIDTH     :integer := 5; 
       WORD_WIDTH    :integer := 32 
   ); 
   port( 
       I             :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
       Q             :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
       z             :out std_logic_vector(EXP_WIDTH-1 downto 0) 
   ); 
end gen_exp_IQ; 
 
architecture rtl of gen_exp_IQ is 
 
    component gen_exp 
    generic( 
        EXP_WIDTH    :integer; 
        WORD_WIDTH   :integer 
    ); 
    port( 
        a            :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        z            :out std_logic_vector(EXP_WIDTH-1 downto 0) 
    ); 
    end component; 
 
    signal exp_I     :std_logic_vector(EXP_WIDTH-1 downto 0); 
    signal exp_Q     :std_logic_vector(EXP_WIDTH-1 downto 0); 
 
begin 
 
    I_exp:gen_exp 
    generic map(EXP_WIDTH => EXP_WIDTH, 
                WORD_WIDTH => WORD_WIDTH) 
    port map( 
        a => I, 
        z => exp_I 
    ); 
 
    Q_exp:gen_exp 
    generic map(EXP_WIDTH => EXP_WIDTH, 
                WORD_WIDTH => WORD_WIDTH) 
    port map( 
        a => Q, 
        z => exp_Q 
    ); 
 
    process(exp_I,exp_Q) 
    begin 
        if (exp_I > exp_Q) then 
           z <= exp_I; 
        else 
           z <= exp_Q; 
        end if; 
    end process; 
 
end rtl;