www.pudn.com > jaguar2s.zip > gen_exp.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                              :1.0                | 
--*|Date of Last Revision                :12/23/1998         | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library ieee; 
use ieee.std_logic_1164.all; 
 
-- determine magnitude of value by looking for first change in MSB 
 
entity gen_exp is 
   generic( 
       EXP_WIDTH      :integer := 5; 
       WORD_WIDTH     :integer := 32 
   ); 
   port( 
       a              :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
       z              :out std_logic_vector(EXP_WIDTH-1 downto 0) 
   ); 
end gen_exp; 
 
architecture rtl of gen_exp is 
 
   signal atmp        :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal ctmp        :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal dtmp        :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
 
begin 
 
    atmp <= '0' & (a(WORD_WIDTH/2-1 downto 1) xor 
                   a(WORD_WIDTH/2-2 downto 0)); 
 
    -- backfill all LSB with one after first toggle bit 
    process(atmp) 
        variable i,j     :integer; 
        variable btmp    :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
    begin 
        for i in 0 to WORD_WIDTH/2-1 loop 
            btmp(WORD_WIDTH/2-1-i):='0'; 
            for j in 0 to i loop 
                btmp(WORD_WIDTH/2-1-i) := btmp(WORD_WIDTH/2-1-i) or 
					            atmp(WORD_WIDTH/2-1-j); 
            end loop;--j 
        end loop;--i 
        ctmp <= btmp; 
    end process; 
 
    dtmp <= '0' & (ctmp(WORD_WIDTH/2-1 downto 1) xor 
                   ctmp(WORD_WIDTH/2-2 downto 0)); 
 
    process(dtmp) 
        variable i,j,k   :integer; 
        variable pow2    :integer; 
        variable ztmp    :std_logic_vector(EXP_WIDTH-1 downto 0); 
    begin 
        pow2:= 1; 
        for i in 0 to EXP_WIDTH-1 loop 
            ztmp(i) := '0'; 
            for j in 0 to (WORD_WIDTH/2-1)/(2*pow2) loop 
                for k in 0 to pow2-1 loop 
                    if (j*(2*pow2)+k+(pow2-1) <= WORD_WIDTH/2-1) then 
                       ztmp(i) := ztmp(i) or  
                                  dtmp(j*(2*pow2)+k+(pow2-1)); 
                    end if; 
                end loop; 
            end loop; 
            pow2:=pow2*2; 
        end loop; 
        z <= ztmp; 
    end process; 
 
end rtl;