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--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                              :1.0                | 
--*|Date of Last Revision                :12/23/1998         | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_signed.all; 
  
-- This entity has an attentuation of 1 bits. 
-- This entity has a delay of 2 clock cycles. 
 
entity fft_mult is 
    generic( 
        WORD_WIDTH   :integer := 32 
    ); 
    port( 
        clk          :in std_logic; 
        fwd          :in std_logic; 
        sin_w        :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        cos_w        :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        X            :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        Y            :out std_logic_vector(WORD_WIDTH-1 downto 0) 
    ); 
end fft_mult; 
 
architecture rtl of fft_mult is 
 
   component signed_add 
      generic( 
          WIDTH      :integer 
      ); 
      port( 
          a          :in std_logic_vector(WIDTH-1 downto 0); 
          b          :in std_logic_vector(WIDTH-1 downto 0); 
          c          :out std_logic_vector(WIDTH-1 downto 0) 
      ); 
   end component;   
 
   component signed_sub 
      generic( 
          WIDTH      :integer 
      ); 
      port( 
          a          :in std_logic_vector(WIDTH-1 downto 0); 
          b          :in std_logic_vector(WIDTH-1 downto 0); 
          c          :out std_logic_vector(WIDTH-1 downto 0) 
      ); 
   end component;   
 
   signal x_i        :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal x_q        :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal sin_w_reg  :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal cos_w_reg  :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
 
   signal A          :std_logic_vector(WORD_WIDTH-1 downto 0); 
   signal B          :std_logic_vector(WORD_WIDTH-1 downto 0); 
   signal C          :std_logic_vector(WORD_WIDTH-1 downto 0); 
   signal D          :std_logic_vector(WORD_WIDTH-1 downto 0); 
   signal E          :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal F          :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal G          :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal H          :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal sum        :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
   signal diff       :std_logic_vector(WORD_WIDTH/2-1 downto 0); 
 
begin  
         
   process 
   begin 
       wait until clk'event and clk = '1'; 
       x_i <= X(WORD_WIDTH-1 downto WORD_WIDTH/2); 
       x_q <= X(WORD_WIDTH/2-1 downto 0); 
       sin_w_reg <= sin_w; 
       cos_w_reg <= cos_w; 
   end process; 
 
   process  
   begin 
       wait until clk'event and clk= '1'; 
       A <= x_i * cos_w_reg; 
       B <= x_q * sin_w_reg; 
       C <= x_q * cos_w_reg; 
       D <= x_i * sin_w_reg; 
   end process; 
 
   process(fwd,A,B,C,D) 
   begin 
      if (fwd = '1') then 
          E <= A(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
          F <= B(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
          G <= C(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
          H <= D(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
      else 
          E <= C(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
          F <= D(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
          G <= A(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
          H <= B(WORD_WIDTH-2 downto WORD_WIDTH/2-1); 
      end if; 
   end process; 
 
   s1_add:signed_add 
       generic map(WIDTH => WORD_WIDTH/2) 
       port map( 
           a => E, 
           b => F, 
           c => sum 
       ); 
 
   s2_sub:signed_sub 
       generic map(WIDTH => WORD_WIDTH/2) 
       port map( 
           a => G, 
           b => H, 
           c => diff 
       ); 
 
   process(fwd,sum,diff) 
   begin 
      if (fwd = '1') then 
          Y(WORD_WIDTH-1 downto WORD_WIDTH/2) <= sum; -- I 
          Y(WORD_WIDTH/2-1 downto 0) <= diff;         -- Q 
      else 
          Y(WORD_WIDTH-1 downto WORD_WIDTH/2) <= diff;-- I 
          Y(WORD_WIDTH/2-1 downto 0) <= sum;          -- Q 
      end if; 
   end process; 
  
end rtl;