www.pudn.com > jaguar2s.zip > compute_pow.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                              :1.0                | 
--*|Date of Last Revision                :12/23/1998         | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
 
entity compute_pow is 
    generic( 
        EXP_WIDTH       :integer := 5 
    ); 
    port( 
        reset           :in std_logic; 
        fwd             :in std_logic; 
        N_select        :in std_logic_vector(2 downto 0); 
        core_clk        :in std_logic; 
        startp          :in std_logic; 
        en_inp_exp      :in std_logic; 
        en_rad_exp      :in std_logic; 
        input_exp       :in std_logic_vector(EXP_WIDTH-1 downto 0); 
        rad_exp         :in std_logic_vector(EXP_WIDTH-1 downto 0); 
        pow_exp         :out std_logic_vector(EXP_WIDTH downto 0) 
    ); 
end compute_pow; 
 
architecture rtl of compute_pow is 
 
    --static attenuation adjustment 
    signal FFT_ATTENUATION     :std_logic_vector(EXP_WIDTH+4 downto 0); 
    signal IFFT_ATTENUATION     :std_logic_vector(EXP_WIDTH+4 downto 0); 
     
    signal new_exp             :std_logic_vector(EXP_WIDTH+4 downto 0); 
    signal accum               :std_logic_vector(EXP_WIDTH+4 downto 0); 
    signal dlyd_en_rad_exp     :std_logic; 
 
begin 
 
    process(N_select) 
    begin 
        case N_select is 
            when "000" => -- 8 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(5,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(8,EXP_WIDTH+5); 
            when "001" => --16 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(7,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(11,EXP_WIDTH+5); 
            when "010" => -- 32 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(9,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(14,EXP_WIDTH+5); 
            when "011" => -- 64 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(11,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(17,EXP_WIDTH+5); 
           when "100" => -- 128 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(13,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(20,EXP_WIDTH+5); 
            when "101" => -- 256 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(15,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(23,EXP_WIDTH+5); 
            when "110" => -- 512 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(17,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(26,EXP_WIDTH+5); 
           when others => -- 1024 pt 
                 FFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(19,EXP_WIDTH+5); 
                 IFFT_ATTENUATION <= CONV_STD_LOGIC_VECTOR(29,EXP_WIDTH+5); 
       end case; 
    end process; 
 
    process 
    begin 
        wait until core_clk'event and core_clk='1'; 
        if (startp = '1') then 
             pow_exp <= new_exp(EXP_WIDTH downto 0); 
        end if; 
    end process; 
 
    process 
    begin 
        wait until core_clk'event and core_clk='1'; 
        dlyd_en_rad_exp <= en_rad_exp; 
    end process; 
     
    process(fwd,accum,FFT_ATTENUATION,IFFT_ATTENUATION) 
    begin 
        if (fwd = '1') then 
            new_exp <= accum - FFT_ATTENUATION; 
        else 
            new_exp <= accum - IFFT_ATTENUATION; 
        end if; 
    end process; 
 
    process(reset,core_clk) 
    begin 
        if (reset = '0') then 
            accum <= (others => '0'); 
        elsif core_clk'event and core_clk='1' then 
            if (en_inp_exp = '1') then 
                 accum <= "00000" & input_exp; 
            elsif (dlyd_en_rad_exp = '1') then 
                 accum <= accum + rad_exp; 
            end if; 
        end if; 
    end process; 
 
end rtl;