www.pudn.com > jaguar2s.zip > compute_input_exp.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                             :1.0                 | 
--*|Date of Last Revision               :12/23/1998          | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all; 
 
entity compute_input_exp is 
    generic( 
        EXP_WIDTH      :integer := 5; 
        WORD_WIDTH     :integer := 32 
    ); 
    port( 
        reset          :in std_logic; 
        clk            :in std_logic; 
        startp         :in std_logic; 
        smplin_we      :in std_logic; 
        smplin_I       :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        smplin_Q       :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        shift_val      :out std_logic_vector(EXP_WIDTH-1 downto 0) 
    ); 
end compute_input_exp; 
 
architecture rtl of compute_input_exp is 
 
    component gen_exp_IQ 
    generic( 
        EXP_WIDTH     :integer; 
        WORD_WIDTH    :integer 
    ); 
    port( 
        I             :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        Q             :in std_logic_vector(WORD_WIDTH/2-1 downto 0); 
        z             :out std_logic_vector(EXP_WIDTH-1 downto 0) 
    ); 
    end component; 
 
    signal exp        :std_logic_vector(EXP_WIDTH-1 downto 0); 
    signal exp_IQ     :std_logic_vector(EXP_WIDTH-1 downto 0); 
 
begin 
 
    exp_gen:gen_exp_IQ 
    generic map(EXP_WIDTH => EXP_WIDTH, 
                WORD_WIDTH => WORD_WIDTH) 
    port map( 
        I => smplin_I, 
        Q => smplin_Q, 
        z => exp_IQ 
    ); 
 
    process(reset,clk) 
    begin 
        if (reset = '0') then 
            shift_val <= (others => '0'); 
        elsif clk'event and clk = '1' then 
            if (startp = '1') then 
                shift_val <= CONV_STD_LOGIC_VECTOR(WORD_WIDTH/2-1,EXP_WIDTH) - exp; 
                          -- convert from mag to shift value 
            end if; 
        end if; 
    end process; 
 
    process(reset,clk) 
    begin 
        if (reset = '0') then 
            exp <= (others => '0'); 
        elsif clk'event and clk = '1' then 
            if (startp = '1') then 
                exp <= (others => '0'); 
            elsif (smplin_we = '1') then 
                if (exp_IQ > exp) then -- look for biggest magnitude 
                    exp <= exp_IQ; 
                end if; 
            end if; 
        end if; 
    end process; 
 
end rtl;