www.pudn.com > jaguar2s.zip > compute_exp.vhd
--************************************************************
--************************************************************
--*----------------------------------------------------------*
--*|Version :1.0 |
--*|Date of Last Revision :12/23/1998 |
--*----------------------------------------------------------*
--************************************************************
-- Copyright (C) 1999 Drey Enterprises Inc. All Rights Reserved.
--************************************************************
-- Warning: This file is protected by Federal Copyright Law,
-- with all rights reserved. It is unlawful to reproduce
-- any parts of this file, in any form, without expressed
-- written permission from Drey Enterprises Inc. This Copyright
-- is actively enforced.
--************************************************************
--************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity compute_exp is
generic(
EXP_WIDTH :integer := 5;
WORD_WIDTH :integer := 32
);
port(
reset :in std_logic;
core_clk :in std_logic;
null_pass :in std_logic;
en_exp :in std_logic;
we :in std_logic;
data0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
data3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb0 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb1 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb2 :in std_logic_vector(WORD_WIDTH-1 downto 0);
datb3 :in std_logic_vector(WORD_WIDTH-1 downto 0);
exp :out std_logic_vector(EXP_WIDTH-1 downto 0)
);
end compute_exp;
architecture rtl of compute_exp is
component gen_exp_IQ
generic(
EXP_WIDTH :integer;
WORD_WIDTH :integer
);
port(
I :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
Q :in std_logic_vector(WORD_WIDTH/2-1 downto 0);
z :out std_logic_vector(EXP_WIDTH-1 downto 0)
);
end component;
signal exp_reg :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQ :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa0 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa1 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa2 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa3 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa01 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa23 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQa :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb0 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb1 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb2 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb3 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb01 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb23 :std_logic_vector(EXP_WIDTH-1 downto 0);
signal exp_IQb :std_logic_vector(EXP_WIDTH-1 downto 0);
begin
exp_a0:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => data0(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => data0(WORD_WIDTH/2-1 downto 0),
z => exp_IQa0
);
exp_a1:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => data1(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => data1(WORD_WIDTH/2-1 downto 0),
z => exp_IQa1
);
exp_a2:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => data2(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => data2(WORD_WIDTH/2-1 downto 0),
z => exp_IQa2
);
exp_a3:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => data3(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => data3(WORD_WIDTH/2-1 downto 0),
z => exp_IQa3
);
exp_b0:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => datb0(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => datb0(WORD_WIDTH/2-1 downto 0),
z => exp_IQb0
);
exp_b1:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => datb1(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => datb1(WORD_WIDTH/2-1 downto 0),
z => exp_IQb1
);
exp_b2:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => datb2(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => datb2(WORD_WIDTH/2-1 downto 0),
z => exp_IQb2
);
exp_b3:gen_exp_IQ
generic map(EXP_WIDTH => EXP_WIDTH,
WORD_WIDTH => WORD_WIDTH)
port map(
I => datb3(WORD_WIDTH-1 downto WORD_WIDTH/2),
Q => datb3(WORD_WIDTH/2-1 downto 0),
z => exp_IQb3
);
-- find the largest of the four
process(exp_IQa0,exp_IQa1,exp_IQa2,exp_IQa3)
begin
if (exp_IQa0 > exp_IQa1) then
exp_IQa01 <= exp_IQa0;
else
exp_IQa01 <= exp_IQa1;
end if;
if (exp_IQa2 > exp_IQa3) then
exp_IQa23 <= exp_IQa2;
else
exp_IQa23 <= exp_IQa3;
end if;
end process;
-- find the largest of the four
process(exp_IQb0,exp_IQb1,exp_IQb2,exp_IQb3)
begin
if (exp_IQb0 > exp_IQb1) then
exp_IQb01 <= exp_IQb0;
else
exp_IQb01 <= exp_IQb1;
end if;
if (exp_IQb2 > exp_IQb3) then
exp_IQb23 <= exp_IQb2;
else
exp_IQb23 <= exp_IQb3;
end if;
end process;
process(exp_IQa01,exp_IQa23,exp_IQb01,exp_IQb23)
begin
if (exp_IQa01 > exp_IQa23) then
exp_IQa <= exp_IQa01;
else
exp_IQa <= exp_IQa23;
end if;
if (exp_IQb01 > exp_IQb23) then
exp_IQb <= exp_IQb01;
else
exp_IQb <= exp_IQb23;
end if;
end process;
process(exp_IQa,exp_IQb)
begin
if (exp_IQa > exp_IQb) then
exp_IQ <= exp_IQa;
else
exp_IQ <= exp_IQb;
end if;
end process;
process(reset,core_clk)
begin
if (reset = '0') then
exp <= (others => '0');
elsif core_clk'event and core_clk = '1' then
if (en_exp = '1') then
if (null_pass = '1') then
exp <= (others => '0');
else
exp <= CONV_STD_LOGIC_VECTOR(WORD_WIDTH/2-1,EXP_WIDTH)
- exp_reg; -- convert from mag to shift value
end if;
end if;
end if;
end process;
process(reset,core_clk)
begin
if (reset = '0') then
exp_reg <= (others => '0');
elsif core_clk'event and core_clk = '1' then
if (en_exp = '1') then
exp_reg <= (others => '0');
elsif (we = '1') then
if (exp_IQ > exp_reg) then -- look for biggest magnitude
exp_reg <= exp_IQ;
end if;
end if;
end if;
end process;
end rtl;