www.pudn.com > jaguar2s.zip > Ram2rw4x256xM.vhd

--************************************************************ 
--************************************************************ 
--*----------------------------------------------------------* 
--*|Version                               :2.0               | 
--*|Date of Last Revision                 :02/23/2001        | 
--*----------------------------------------------------------* 
--************************************************************ 
-- Copyright (C) 1999 Drey Enterprises Inc.   All Rights Reserved. 
--************************************************************ 
-- Warning: This file is protected by Federal Copyright Law, 
-- with all rights reserved. It is unlawful to reproduce 
-- any parts of this file, in any form, without expressed 
-- written permission from Drey Enterprises Inc. This Copyright 
-- is actively enforced. 
--************************************************************ 
--************************************************************ 
 
library IEEE; 
use IEEE.std_logic_1164.all; 
 
-- Four 2port RAMS of variable width 
  
entity RAM2RW4x256xM is 
    generic( 
        WORD_WIDTH       :integer := 32 
    ); 
    port ( 
        clk              :in std_logic; 
        pass             :in std_logic_vector(3 downto 0); 
        wea0             :in std_logic; 
        web0             :in std_logic; 
        addra0           :in std_logic_vector(7 downto 0); 
        addrb0           :in std_logic_vector(7 downto 0); 
        dataina0         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        datainb0         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataouta0        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataoutb0        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        wea1             :in std_logic; 
        web1             :in std_logic; 
        addra1           :in std_logic_vector(7 downto 0); 
        addrb1           :in std_logic_vector(7 downto 0); 
        dataina1         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        datainb1         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataouta1        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataoutb1        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        wea2             :in std_logic; 
        web2             :in std_logic; 
        addra2           :in std_logic_vector(7 downto 0); 
        addrb2           :in std_logic_vector(7 downto 0); 
        dataina2         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        datainb2         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataouta2        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataoutb2        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        wea3             :in std_logic; 
        web3             :in std_logic; 
        addra3           :in std_logic_vector(7 downto 0); 
        addrb3           :in std_logic_vector(7 downto 0); 
        dataina3         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        datainb3         :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataouta3        :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataoutb3        :out std_logic_vector(WORD_WIDTH-1 downto 0) 
     ); 
end RAM2RW4x256xM; 
 
architecture structure of RAM2RW4x256xM is 
 
    component RAM2RW256xM 
    generic( 
        WORD_WIDTH       :integer); 
    port( 
        clk              :in std_logic; 
        pass             :in std_logic_vector(3 downto 0); 
        wea              :in std_logic; 
        web              :in std_logic; 
        addra            :in std_logic_vector(7 downto 0); 
        addrb            :in std_logic_vector(7 downto 0); 
        dataina          :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        datainb          :in std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataouta         :out std_logic_vector(WORD_WIDTH-1 downto 0); 
        dataoutb         :out std_logic_vector(WORD_WIDTH-1 downto 0) 
    ); 
    end component; 
     
begin 
 
    ram0:RAM2RW256xM 
    generic map(WORD_WIDTH => WORD_WIDTH) 
    port map( 
        clk => clk, 
        pass => pass, 
        wea => wea0, 
        web => web0, 
        addra => addra0, 
        addrb => addrb0, 
        dataina => dataina0, 
        datainb => datainb0, 
        dataouta => dataouta0, 
        dataoutb => dataoutb0 
    ); 
 
    ram1:RAM2RW256xM 
    generic map(WORD_WIDTH => WORD_WIDTH) 
    port map( 
        clk => clk, 
        pass => pass, 
        wea => wea1, 
        web => web1, 
        addra => addra1, 
        addrb => addrb1, 
        dataina => dataina1, 
        datainb => datainb1, 
        dataouta => dataouta1, 
        dataoutb => dataoutb1 
    ); 
 
    ram2:RAM2RW256xM 
    generic map(WORD_WIDTH => WORD_WIDTH) 
    port map( 
        clk => clk, 
        pass => pass, 
        wea => wea2, 
        web => web2, 
        addra => addra2, 
        addrb => addrb2, 
        dataina => dataina2, 
        datainb => datainb2, 
        dataouta => dataouta2, 
        dataoutb => dataoutb2 
    ); 
 
    ram3:RAM2RW256xM 
    generic map(WORD_WIDTH => WORD_WIDTH) 
    port map( 
        clk => clk, 
        pass => pass, 
        wea => wea3, 
        web => web3, 
        addra => addra3, 
        addrb => addrb3, 
        dataina => dataina3, 
        datainb => datainb3, 
        dataouta => dataouta3, 
        dataoutb => dataoutb3 
    ); 
 
end structure;