www.pudn.com > jaguar2s.zip > compile_jag2.tcl

rm syn_work/* 
 
dc_shell << ! 
 
define_design_lib syn_work -path ./syn_work 
define_design_lib des_lib -path #### Put path to vendor libs here #### 
 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/cosrom128_w1.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/sinrom128_w1.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/cosrom256_w1.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/cosrom256_w2.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/cosrom256_w3.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/sinrom256_w1.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/sinrom256_w2.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/sinrom256_w3.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/sincos_rom_256.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/roms/sincos_rom_128.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/signed_add.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/signed_sub.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/signed_addf.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/signed_subf.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/Lshifter.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/fft_mult.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/scaling.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/gen_exp.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/gen_exp_IQ.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/output_scaling.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/compute_pow.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/compute_exp.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/compute_input_exp.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad2_romaddr_cmpt.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad4_romaddr_cmpt.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad2_oram_addr_cmpt_last.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad2_addr_cmpt.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad2_4_eval.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad2_sqncr.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/rad4_sqncr.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/radix2.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/radix2_4.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/sequencer.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/Ram2rw4x256xM.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/input_ram_bank.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/output_ram_bank.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/jaguar2.vhd 
analyze -f vhdl -work syn_work /home/dreyent/designs/jaguar2/jaguar2_io.vhd 
 
 
elaborate  -work syn_work  jaguar2_io       > logs/elab_jaguar2.log 
check_design                                > logs/chk_jaguar2.log 
link                                        > logs/link_jaguar2.log 
 
write_file -format db -hierarchy -output jaguar2_netlist_premap.db 
write_file -format vhdl -hierarchy -output jaguar2_netlist_premap.vhd 
 
uniquify 
 
set_flatten false 
set_structure true  -boolean false -timing true 
compile_preserve_sync_resets = "true" 
compile_use_fast_delay_mode = "true" 
set_scan_configuration -style multiplexed_flip_flop -methodology full_scan 
 
create_clock -name "core_clk_pin" -period 10  -waveform {"0" "5"} {"core_clk_pin"}  
set_clock_skew -uncertainty 1.0 {core_clk_pin} 
 
set_resource_allocation area_only 
 
compile  -map_effort low -area_effort low -no_design_rule 
report_reference > logs/jaguar2_report_reference.txt 
check_design > logs/jaguar2_check_design.txt 
report_constraint > logs/jaguar2_constraint_report.txt 
 
write_file -format db -hierarchy -output jaguar2_netlist_postmap.db 
write_file -format vhdl -hierarchy -output jaguar2_netlist_postmap.vhd 
 
!