www.pudn.com > ucosforcodewarrior-hc12.rar > IO_Map.c, change:2006-01-03,size:43251b


/** ################################################################### 
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT. 
**     Filename  : IO_Map.C 
**     Project   : _2006_01_02_PE 
**     Processor : MC9S12H256CPV 
**     Beantype  : IO_Map 
**     Version   : Driver 01.03 
**     Compiler  : Metrowerks HC12 C Compiler 
**     Date/Time : 1/3/2006, 3:21 PM 
**     Abstract  : 
**         IO_Map.h - implements an IO device's mapping.  
**         This module contains symbol definitions of all peripheral  
**         registers and bits.  
**     Settings  : 
** 
**     Contents  : 
**         No public methods 
** 
**     (c) Copyright UNIS, spol. s r.o. 1997-2004 
**     UNIS, spol. s r.o. 
**     Jundrovska 33 
**     624 00 Brno 
**     Czech Republic 
**     http      : www.processorexpert.com 
**     mail      : info@processorexpert.com 
** ###################################################################*/ 
/* Based on CPU DB MC9S12H256_112, version 2.87.329 (RegistersPrg V1.097) */ 
/* DataSheet : 9S12H256BDGV1/D V01.16 */ 
 
#include "PE_types.h" 
#include "IO_Map.h" 
 
 
/* * * * *  8-BIT REGISTERS  * * * * * * * * * * * * * * * */ 
volatile PORTESTR _PORTE @(REG_BASE + 0x00000008);         /* Port E Register; 0x00000008 */ 
volatile DDRESTR _DDRE @(REG_BASE + 0x00000009);           /* Port E Data Direction Register; 0x00000009 */ 
volatile PEARSTR _PEAR @(REG_BASE + 0x0000000A);           /* Port E Assignment Register; 0x0000000A */ 
volatile MODESTR _MODE @(REG_BASE + 0x0000000B);           /* Mode Register; 0x0000000B */ 
volatile PUCRSTR _PUCR @(REG_BASE + 0x0000000C);           /* Pull-Up Control Register; 0x0000000C */ 
volatile RDRIVSTR _RDRIV @(REG_BASE + 0x0000000D);         /* Reduced Drive of I/O Lines; 0x0000000D */ 
volatile EBICTLSTR _EBICTL @(REG_BASE + 0x0000000E);       /* External Bus Interface Control; 0x0000000E */ 
volatile INITRMSTR _INITRM @(REG_BASE + 0x00000010);       /* Initialization of Internal RAM Position Register; 0x00000010 */ 
volatile INITRGSTR _INITRG @(REG_BASE + 0x00000011);       /* Initialization of Internal Registers Position Register; 0x00000011 */ 
volatile INITEESTR _INITEE @(REG_BASE + 0x00000012);       /* Initialization of Internal EEPROM Position Register; 0x00000012 */ 
volatile MISCSTR _MISC @(REG_BASE + 0x00000013);           /* Miscellaneous System Control Register; 0x00000013 */ 
volatile ITCRSTR _ITCR @(REG_BASE + 0x00000015);           /* Interrupt Test Control Register; 0x00000015 */ 
volatile ITESTSTR _ITEST @(REG_BASE + 0x00000016);         /* Interrupt Test Register; 0x00000016 */ 
volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);     /* Memory Size Register Zero; 0x0000001C */ 
volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);     /* Memory Size Register One; 0x0000001D */ 
volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);         /* Interrupt Control Register; 0x0000001E */ 
volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);         /* Highest Priority I Interrupt; 0x0000001F */ 
volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);       /* Breakpoint Control Register 0; 0x00000028 */ 
volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);       /* Breakpoint Control Register 1; 0x00000029 */ 
volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);         /* First Address Memory Expansion Breakpoint Register; 0x0000002A */ 
volatile BKP0HSTR _BKP0H @(REG_BASE + 0x0000002B);         /* First Address High Byte Breakpoint Register; 0x0000002B */ 
volatile BKP0LSTR _BKP0L @(REG_BASE + 0x0000002C);         /* First Address Low Byte Breakpoint Register; 0x0000002C */ 
volatile BKP1XSTR _BKP1X @(REG_BASE + 0x0000002D);         /* Second Address Memory Expansion Breakpoint Register; 0x0000002D */ 
volatile BKP1HSTR _BKP1H @(REG_BASE + 0x0000002E);         /* Data (Second Address) High Byte Breakpoint Register; 0x0000002E */ 
volatile BKP1LSTR _BKP1L @(REG_BASE + 0x0000002F);         /* Data (Second Address) Low Byte Breakpoint Register; 0x0000002F */ 
volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000030);         /* Page Index Register; 0x00000030 */ 
volatile PORTKSTR _PORTK @(REG_BASE + 0x00000032);         /* Port K Data Register; 0x00000032 */ 
volatile DDRKSTR _DDRK @(REG_BASE + 0x00000033);           /* Port K Data Direction Register; 0x00000033 */ 
volatile SYNRSTR _SYNR @(REG_BASE + 0x00000034);           /* CRG Synthesizer Register; 0x00000034 */ 
volatile REFDVSTR _REFDV @(REG_BASE + 0x00000035);         /* CRG Reference Divider Register; 0x00000035 */ 
volatile CRGFLGSTR _CRGFLG @(REG_BASE + 0x00000037);       /* CRG Flags Register; 0x00000037 */ 
volatile CRGINTSTR _CRGINT @(REG_BASE + 0x00000038);       /* CRG Interrupt Enable Register; 0x00000038 */ 
volatile CLKSELSTR _CLKSEL @(REG_BASE + 0x00000039);       /* CRG Clock Select Register; 0x00000039 */ 
volatile PLLCTLSTR _PLLCTL @(REG_BASE + 0x0000003A);       /* CRG PLL Control Register; 0x0000003A */ 
volatile RTICTLSTR _RTICTL @(REG_BASE + 0x0000003B);       /* CRG RTI Control Register; 0x0000003B */ 
volatile COPCTLSTR _COPCTL @(REG_BASE + 0x0000003C);       /* CRG COP Control Register; 0x0000003C */ 
volatile ARMCOPSTR _ARMCOP @(REG_BASE + 0x0000003F);       /* CRG COP Timer Arm/Reset Register; 0x0000003F */ 
volatile TIOSSTR _TIOS @(REG_BASE + 0x00000040);           /* Timer Input Capture/Output Compare Select; 0x00000040 */ 
volatile CFORCSTR _CFORC @(REG_BASE + 0x00000041);         /* Timer Compare Force Register; 0x00000041 */ 
volatile OC7MSTR _OC7M @(REG_BASE + 0x00000042);           /* Output Compare 7 Mask Register; 0x00000042 */ 
volatile OC7DSTR _OC7D @(REG_BASE + 0x00000043);           /* Output Compare 7 Data Register; 0x00000043 */ 
volatile TSCR1STR _TSCR1 @(REG_BASE + 0x00000046);         /* Timer System Control Register1; 0x00000046 */ 
volatile TTOVSTR _TTOV @(REG_BASE + 0x00000047);           /* Timer Toggle On Overflow Register; 0x00000047 */ 
volatile TCTL1STR _TCTL1 @(REG_BASE + 0x00000048);         /* Timer Control Register 1; 0x00000048 */ 
volatile TCTL2STR _TCTL2 @(REG_BASE + 0x00000049);         /* Timer Control Register 2; 0x00000049 */ 
volatile TCTL3STR _TCTL3 @(REG_BASE + 0x0000004A);         /* Timer Control Register 3; 0x0000004A */ 
volatile TCTL4STR _TCTL4 @(REG_BASE + 0x0000004B);         /* Timer Control Register 4; 0x0000004B */ 
volatile TIESTR _TIE @(REG_BASE + 0x0000004C);             /* Timer Interrupt Enable Register; 0x0000004C */ 
volatile TSCR2STR _TSCR2 @(REG_BASE + 0x0000004D);         /* Timer System Control Register 2; 0x0000004D */ 
volatile TFLG1STR _TFLG1 @(REG_BASE + 0x0000004E);         /* Main Timer Interrupt Flag 1; 0x0000004E */ 
volatile TFLG2STR _TFLG2 @(REG_BASE + 0x0000004F);         /* Main Timer Interrupt Flag 2; 0x0000004F */ 
volatile PACTLSTR _PACTL @(REG_BASE + 0x00000060);         /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */ 
volatile PAFLGSTR _PAFLG @(REG_BASE + 0x00000061);         /* Pulse Accumulator A Flag Register; 0x00000061 */ 
volatile ATDSTAT0STR _ATDSTAT0 @(REG_BASE + 0x00000086);   /* ATD Status Register 0; 0x00000086 */ 
volatile ATDTEST1STR _ATDTEST1 @(REG_BASE + 0x00000089);   /* ATD Test Register; 0x00000089 */ 
volatile ATDSTAT2STR _ATDSTAT2 @(REG_BASE + 0x0000008A);   /* ATD Status Register 2; 0x0000008A */ 
volatile ATDSTAT1STR _ATDSTAT1 @(REG_BASE + 0x0000008B);   /* ATD Status Register 1; 0x0000008B */ 
volatile IBADSTR _IBAD @(REG_BASE + 0x000000C0);           /* IIC Address Register; 0x000000C0 */ 
volatile IBFDSTR _IBFD @(REG_BASE + 0x000000C1);           /* IIC Frequency Divider Register; 0x000000C1 */ 
volatile IBCRSTR _IBCR @(REG_BASE + 0x000000C2);           /* IIC Control Register; 0x000000C2 */ 
volatile IBSRSTR _IBSR @(REG_BASE + 0x000000C3);           /* IIC Status Register; 0x000000C3 */ 
volatile IBDRSTR _IBDR @(REG_BASE + 0x000000C4);           /* IIC Data I/O Register; 0x000000C4 */ 
volatile SCI0CR1STR _SCI0CR1 @(REG_BASE + 0x000000CA);     /* SCI 0 Control Register 1; 0x000000CA */ 
volatile SCI0CR2STR _SCI0CR2 @(REG_BASE + 0x000000CB);     /* SCI 0 Control Register 2; 0x000000CB */ 
volatile SCI0SR1STR _SCI0SR1 @(REG_BASE + 0x000000CC);     /* SCI 0 Status Register 1; 0x000000CC */ 
volatile SCI0SR2STR _SCI0SR2 @(REG_BASE + 0x000000CD);     /* SCI 0 Status Register 2; 0x000000CD */ 
volatile SCI0DRHSTR _SCI0DRH @(REG_BASE + 0x000000CE);     /* SCI 0 Data Register High; 0x000000CE */ 
volatile SCI0DRLSTR _SCI0DRL @(REG_BASE + 0x000000CF);     /* SCI 0 Data Register Low; 0x000000CF */ 
volatile SCI1CR1STR _SCI1CR1 @(REG_BASE + 0x000000D2);     /* SCI 1 Control Register 1; 0x000000D2 */ 
volatile SCI1CR2STR _SCI1CR2 @(REG_BASE + 0x000000D3);     /* SCI 1 Control Register 2; 0x000000D3 */ 
volatile SCI1SR1STR _SCI1SR1 @(REG_BASE + 0x000000D4);     /* SCI 1 Status Register 1; 0x000000D4 */ 
volatile SCI1SR2STR _SCI1SR2 @(REG_BASE + 0x000000D5);     /* SCI 1 Status Register 2; 0x000000D5 */ 
volatile SCI1DRHSTR _SCI1DRH @(REG_BASE + 0x000000D6);     /* SCI 1 Data Register High; 0x000000D6 */ 
volatile SCI1DRLSTR _SCI1DRL @(REG_BASE + 0x000000D7);     /* SCI 1 Data Register Low; 0x000000D7 */ 
volatile SPICR1STR _SPICR1 @(REG_BASE + 0x000000D8);       /* SPI 0 Control Register; 0x000000D8 */ 
volatile SPICR2STR _SPICR2 @(REG_BASE + 0x000000D9);       /* SPI 0 Control Register 2; 0x000000D9 */ 
volatile SPIBRSTR _SPIBR @(REG_BASE + 0x000000DA);         /* SPI 0 Baud Rate Register; 0x000000DA */ 
volatile SPISRSTR _SPISR @(REG_BASE + 0x000000DB);         /* SPI 0 Status Register; 0x000000DB */ 
volatile SPIDRSTR _SPIDR @(REG_BASE + 0x000000DD);         /* SPI 0 Data Register; 0x000000DD */ 
volatile PWMESTR _PWME @(REG_BASE + 0x000000E0);           /* PWM Enable Register; 0x000000E0 */ 
volatile PWMPOLSTR _PWMPOL @(REG_BASE + 0x000000E1);       /* PWM Polarity Register; 0x000000E1 */ 
volatile PWMCLKSTR _PWMCLK @(REG_BASE + 0x000000E2);       /* PWM Clock Select Register; 0x000000E2 */ 
volatile PWMPRCLKSTR _PWMPRCLK @(REG_BASE + 0x000000E3);   /* PWM Prescale Clock Select Register; 0x000000E3 */ 
volatile PWMCAESTR _PWMCAE @(REG_BASE + 0x000000E4);       /* PWM Center Align Enable Register; 0x000000E4 */ 
volatile PWMCTLSTR _PWMCTL @(REG_BASE + 0x000000E5);       /* PWM Control Register; 0x000000E5 */ 
volatile PWMSCLASTR _PWMSCLA @(REG_BASE + 0x000000E8);     /* PWM Scale A Register; 0x000000E8 */ 
volatile PWMSCLBSTR _PWMSCLB @(REG_BASE + 0x000000E9);     /* PWM Scale B Register; 0x000000E9 */ 
volatile PWMSDNSTR _PWMSDN @(REG_BASE + 0x000000FE);       /* PWM Shutdown Register; 0x000000FE */ 
volatile FCLKDIVSTR _FCLKDIV @(REG_BASE + 0x00000100);     /* Flash Clock Divider Register; 0x00000100 */ 
volatile FSECSTR _FSEC @(REG_BASE + 0x00000101);           /* Flash Security Register; 0x00000101 */ 
volatile FCNFGSTR _FCNFG @(REG_BASE + 0x00000103);         /* Flash Configuration Register; 0x00000103 */ 
volatile FPROTSTR _FPROT @(REG_BASE + 0x00000104);         /* Flash Protection Register; 0x00000104 */ 
volatile FSTATSTR _FSTAT @(REG_BASE + 0x00000105);         /* Flash Status Register; 0x00000105 */ 
volatile FCMDSTR _FCMD @(REG_BASE + 0x00000106);           /* Flash Command Buffer and Register; 0x00000106 */ 
volatile ECLKDIVSTR _ECLKDIV @(REG_BASE + 0x00000110);     /* EEPROM Clock Divider Register; 0x00000110 */ 
volatile ECNFGSTR _ECNFG @(REG_BASE + 0x00000113);         /* EEPROM Configuration Register; 0x00000113 */ 
volatile EPROTSTR _EPROT @(REG_BASE + 0x00000114);         /* EEPROM Protection Register; 0x00000114 */ 
volatile ESTATSTR _ESTAT @(REG_BASE + 0x00000115);         /* EEPROM Status Register; 0x00000115 */ 
volatile ECMDSTR _ECMD @(REG_BASE + 0x00000116);           /* EEPROM Command Buffer and Register; 0x00000116 */ 
volatile LCDCR0STR _LCDCR0 @(REG_BASE + 0x00000120);       /* LCD Control Register 0; 0x00000120 */ 
volatile LCDCR1STR _LCDCR1 @(REG_BASE + 0x00000121);       /* LCD Control Register 1; 0x00000121 */ 
volatile FPENR0STR _FPENR0 @(REG_BASE + 0x00000122);       /* LCD Frontplane Enable Register 0; 0x00000122 */ 
volatile FPENR1STR _FPENR1 @(REG_BASE + 0x00000123);       /* LCD Frontplane Enable Register 1; 0x00000123 */ 
volatile FPENR2STR _FPENR2 @(REG_BASE + 0x00000124);       /* LCD Frontplane Enable Register 2; 0x00000124 */ 
volatile FPENR3STR _FPENR3 @(REG_BASE + 0x00000125);       /* LCD Frontplane Enable Register 3; 0x00000125 */ 
volatile LCDRAM0STR _LCDRAM0 @(REG_BASE + 0x00000128);     /* LCD RAM Register 0; 0x00000128 */ 
volatile LCDRAM1STR _LCDRAM1 @(REG_BASE + 0x00000129);     /* LCD RAM Register 1; 0x00000129 */ 
volatile LCDRAM2STR _LCDRAM2 @(REG_BASE + 0x0000012A);     /* LCD RAM Register 2; 0x0000012A */ 
volatile LCDRAM3STR _LCDRAM3 @(REG_BASE + 0x0000012B);     /* LCD RAM Register 3; 0x0000012B */ 
volatile LCDRAM4STR _LCDRAM4 @(REG_BASE + 0x0000012C);     /* LCD RAM Register 4; 0x0000012C */ 
volatile LCDRAM5STR _LCDRAM5 @(REG_BASE + 0x0000012D);     /* LCD RAM Register 5; 0x0000012D */ 
volatile LCDRAM6STR _LCDRAM6 @(REG_BASE + 0x0000012E);     /* LCD RAM Register 6; 0x0000012E */ 
volatile LCDRAM7STR _LCDRAM7 @(REG_BASE + 0x0000012F);     /* LCD RAM Register 7; 0x0000012F */ 
volatile LCDRAM8STR _LCDRAM8 @(REG_BASE + 0x00000130);     /* LCD RAM Register 8; 0x00000130 */ 
volatile LCDRAM9STR _LCDRAM9 @(REG_BASE + 0x00000131);     /* LCD RAM Register 9; 0x00000131 */ 
volatile LCDRAM10STR _LCDRAM10 @(REG_BASE + 0x00000132);   /* LCD RAM Register 10; 0x00000132 */ 
volatile LCDRAM11STR _LCDRAM11 @(REG_BASE + 0x00000133);   /* LCD RAM Register 11; 0x00000133 */ 
volatile LCDRAM12STR _LCDRAM12 @(REG_BASE + 0x00000134);   /* LCD RAM Register 12; 0x00000134 */ 
volatile LCDRAM13STR _LCDRAM13 @(REG_BASE + 0x00000135);   /* LCD RAM Register 13; 0x00000135 */ 
volatile LCDRAM14STR _LCDRAM14 @(REG_BASE + 0x00000136);   /* LCD RAM Register 14; 0x00000136 */ 
volatile LCDRAM15STR _LCDRAM15 @(REG_BASE + 0x00000137);   /* LCD RAM Register 15; 0x00000137 */ 
volatile CAN0CTL0STR _CAN0CTL0 @(REG_BASE + 0x00000140);   /* MSCAN 0 Control 0 Register; 0x00000140 */ 
volatile CAN0CTL1STR _CAN0CTL1 @(REG_BASE + 0x00000141);   /* MSCAN 0 Control 1 Register; 0x00000141 */ 
volatile CAN0BTR0STR _CAN0BTR0 @(REG_BASE + 0x00000142);   /* MSCAN 0 Bus Timing Register 0; 0x00000142 */ 
volatile CAN0BTR1STR _CAN0BTR1 @(REG_BASE + 0x00000143);   /* MSCAN 0 Bus Timing Register 1; 0x00000143 */ 
volatile CAN0RFLGSTR _CAN0RFLG @(REG_BASE + 0x00000144);   /* MSCAN 0 Receiver Flag Register; 0x00000144 */ 
volatile CAN0RIERSTR _CAN0RIER @(REG_BASE + 0x00000145);   /* MSCAN 0 Receiver Interrupt Enable Register; 0x00000145 */ 
volatile CAN0TFLGSTR _CAN0TFLG @(REG_BASE + 0x00000146);   /* MSCAN 0 Transmitter Flag Register; 0x00000146 */ 
volatile CAN0TIERSTR _CAN0TIER @(REG_BASE + 0x00000147);   /* MSCAN 0 Transmitter Interrupt Enable Register; 0x00000147 */ 
volatile CAN0TARQSTR _CAN0TARQ @(REG_BASE + 0x00000148);   /* MSCAN 0 Transmitter Message Abort Request; 0x00000148 */ 
volatile CAN0TAAKSTR _CAN0TAAK @(REG_BASE + 0x00000149);   /* MSCAN 0 Transmitter Message Abort Control; 0x00000149 */ 
volatile CAN0TBSELSTR _CAN0TBSEL @(REG_BASE + 0x0000014A); /* MSCAN 0 Transmit Buffer Selection; 0x0000014A */ 
volatile CAN0IDACSTR _CAN0IDAC @(REG_BASE + 0x0000014B);   /* MSCAN 0 Identifier Acceptance Control Register; 0x0000014B */ 
volatile CAN0RXERRSTR _CAN0RXERR @(REG_BASE + 0x0000014E); /* MSCAN 0 Receive Error Counter Register; 0x0000014E */ 
volatile CAN0TXERRSTR _CAN0TXERR @(REG_BASE + 0x0000014F); /* MSCAN 0 Transmit Error Counter Register; 0x0000014F */ 
volatile CAN0IDAR0STR _CAN0IDAR0 @(REG_BASE + 0x00000150); /* MSCAN 0 Identifier Acceptance Register 0; 0x00000150 */ 
volatile CAN0IDAR1STR _CAN0IDAR1 @(REG_BASE + 0x00000151); /* MSCAN 0 Identifier Acceptance Register 1; 0x00000151 */ 
volatile CAN0IDAR2STR _CAN0IDAR2 @(REG_BASE + 0x00000152); /* MSCAN 0 Identifier Acceptance Register 2; 0x00000152 */ 
volatile CAN0IDAR3STR _CAN0IDAR3 @(REG_BASE + 0x00000153); /* MSCAN 0 Identifier Acceptance Register 3; 0x00000153 */ 
volatile CAN0IDMR0STR _CAN0IDMR0 @(REG_BASE + 0x00000154); /* MSCAN 0 Identifier Mask Register 0; 0x00000154 */ 
volatile CAN0IDMR1STR _CAN0IDMR1 @(REG_BASE + 0x00000155); /* MSCAN 0 Identifier Mask Register 1; 0x00000155 */ 
volatile CAN0IDMR2STR _CAN0IDMR2 @(REG_BASE + 0x00000156); /* MSCAN 0 Identifier Mask Register 2; 0x00000156 */ 
volatile CAN0IDMR3STR _CAN0IDMR3 @(REG_BASE + 0x00000157); /* MSCAN 0 Identifier Mask Register 3; 0x00000157 */ 
volatile CAN0IDAR4STR _CAN0IDAR4 @(REG_BASE + 0x00000158); /* MSCAN 0 Identifier Acceptance Register 4; 0x00000158 */ 
volatile CAN0IDAR5STR _CAN0IDAR5 @(REG_BASE + 0x00000159); /* MSCAN 0 Identifier Acceptance Register 5; 0x00000159 */ 
volatile CAN0IDAR6STR _CAN0IDAR6 @(REG_BASE + 0x0000015A); /* MSCAN 0 Identifier Acceptance Register 6; 0x0000015A */ 
volatile CAN0IDAR7STR _CAN0IDAR7 @(REG_BASE + 0x0000015B); /* MSCAN 0 Identifier Acceptance Register 7; 0x0000015B */ 
volatile CAN0IDMR4STR _CAN0IDMR4 @(REG_BASE + 0x0000015C); /* MSCAN 0 Identifier Mask Register 4; 0x0000015C */ 
volatile CAN0IDMR5STR _CAN0IDMR5 @(REG_BASE + 0x0000015D); /* MSCAN 0 Identifier Mask Register 5; 0x0000015D */ 
volatile CAN0IDMR6STR _CAN0IDMR6 @(REG_BASE + 0x0000015E); /* MSCAN 0 Identifier Mask Register 6; 0x0000015E */ 
volatile CAN0IDMR7STR _CAN0IDMR7 @(REG_BASE + 0x0000015F); /* MSCAN 0 Identifier Mask Register 7; 0x0000015F */ 
volatile CAN0RXIDR0STR _CAN0RXIDR0 @(REG_BASE + 0x00000160); /* MSCAN 0 Receive Identifier Register 0; 0x00000160 */ 
volatile CAN0RXIDR1STR _CAN0RXIDR1 @(REG_BASE + 0x00000161); /* MSCAN 0 Receive Identifier Register 1; 0x00000161 */ 
volatile CAN0RXIDR2STR _CAN0RXIDR2 @(REG_BASE + 0x00000162); /* MSCAN 0 Receive Identifier Register 2; 0x00000162 */ 
volatile CAN0RXIDR3STR _CAN0RXIDR3 @(REG_BASE + 0x00000163); /* MSCAN 0 Receive Identifier Register 3; 0x00000163 */ 
volatile CAN0RXDSR0STR _CAN0RXDSR0 @(REG_BASE + 0x00000164); /* MSCAN 0 Receive Data Segment Register 0; 0x00000164 */ 
volatile CAN0RXDSR1STR _CAN0RXDSR1 @(REG_BASE + 0x00000165); /* MSCAN 0 Receive Data Segment Register 1; 0x00000165 */ 
volatile CAN0RXDSR2STR _CAN0RXDSR2 @(REG_BASE + 0x00000166); /* MSCAN 0 Receive Data Segment Register 2; 0x00000166 */ 
volatile CAN0RXDSR3STR _CAN0RXDSR3 @(REG_BASE + 0x00000167); /* MSCAN 0 Receive Data Segment Register 3; 0x00000167 */ 
volatile CAN0RXDSR4STR _CAN0RXDSR4 @(REG_BASE + 0x00000168); /* MSCAN 0 Receive Data Segment Register 4; 0x00000168 */ 
volatile CAN0RXDSR5STR _CAN0RXDSR5 @(REG_BASE + 0x00000169); /* MSCAN 0 Receive Data Segment Register 5; 0x00000169 */ 
volatile CAN0RXDSR6STR _CAN0RXDSR6 @(REG_BASE + 0x0000016A); /* MSCAN 0 Receive Data Segment Register 6; 0x0000016A */ 
volatile CAN0RXDSR7STR _CAN0RXDSR7 @(REG_BASE + 0x0000016B); /* MSCAN 0 Receive Data Segment Register 7; 0x0000016B */ 
volatile CAN0RXDLRSTR _CAN0RXDLR @(REG_BASE + 0x0000016C); /* MSCAN 0 Receive Data Length Register; 0x0000016C */ 
volatile CAN0TXIDR0STR _CAN0TXIDR0 @(REG_BASE + 0x00000170); /* MSCAN 0 Transmit Identifier Register 0; 0x00000170 */ 
volatile CAN0TXIDR1STR _CAN0TXIDR1 @(REG_BASE + 0x00000171); /* MSCAN 0 Transmit Identifier Register 1; 0x00000171 */ 
volatile CAN0TXIDR2STR _CAN0TXIDR2 @(REG_BASE + 0x00000172); /* MSCAN 0 Transmit Identifier Register 2; 0x00000172 */ 
volatile CAN0TXIDR3STR _CAN0TXIDR3 @(REG_BASE + 0x00000173); /* MSCAN 0 Transmit Identifier Register 3; 0x00000173 */ 
volatile CAN0TXDSR0STR _CAN0TXDSR0 @(REG_BASE + 0x00000174); /* MSCAN 0 Transmit Data Segment Register 0; 0x00000174 */ 
volatile CAN0TXDSR1STR _CAN0TXDSR1 @(REG_BASE + 0x00000175); /* MSCAN 0 Transmit Data Segment Register 1; 0x00000175 */ 
volatile CAN0TXDSR2STR _CAN0TXDSR2 @(REG_BASE + 0x00000176); /* MSCAN 0 Transmit Data Segment Register 2; 0x00000176 */ 
volatile CAN0TXDSR3STR _CAN0TXDSR3 @(REG_BASE + 0x00000177); /* MSCAN 0 Transmit Data Segment Register 3; 0x00000177 */ 
volatile CAN0TXDSR4STR _CAN0TXDSR4 @(REG_BASE + 0x00000178); /* MSCAN 0 Transmit Data Segment Register 4; 0x00000178 */ 
volatile CAN0TXDSR5STR _CAN0TXDSR5 @(REG_BASE + 0x00000179); /* MSCAN 0 Transmit Data Segment Register 5; 0x00000179 */ 
volatile CAN0TXDSR6STR _CAN0TXDSR6 @(REG_BASE + 0x0000017A); /* MSCAN 0 Transmit Data Segment Register 6; 0x0000017A */ 
volatile CAN0TXDSR7STR _CAN0TXDSR7 @(REG_BASE + 0x0000017B); /* MSCAN 0 Transmit Data Segment Register 7; 0x0000017B */ 
volatile CAN0TXDLRSTR _CAN0TXDLR @(REG_BASE + 0x0000017C); /* MSCAN 0 Transmit Data Length Register; 0x0000017C */ 
volatile CAN0TXTBPRSTR _CAN0TXTBPR @(REG_BASE + 0x0000017D); /* MSCAN 0 Transmit Buffer Priority; 0x0000017D */ 
volatile CAN1CTL0STR _CAN1CTL0 @(REG_BASE + 0x00000180);   /* MSCAN 1 Control 0 Register; 0x00000180 */ 
volatile CAN1CTL1STR _CAN1CTL1 @(REG_BASE + 0x00000181);   /* MSCAN 1 Control 1 Register; 0x00000181 */ 
volatile CAN1BTR0STR _CAN1BTR0 @(REG_BASE + 0x00000182);   /* MSCAN 1 Bus Timing Register 0; 0x00000182 */ 
volatile CAN1BTR1STR _CAN1BTR1 @(REG_BASE + 0x00000183);   /* MSCAN 1 Bus Timing Register 1; 0x00000183 */ 
volatile CAN1RFLGSTR _CAN1RFLG @(REG_BASE + 0x00000184);   /* MSCAN 1 Receiver Flag Register; 0x00000184 */ 
volatile CAN1RIERSTR _CAN1RIER @(REG_BASE + 0x00000185);   /* MSCAN 1 Receiver Interrupt Enable Register; 0x00000185 */ 
volatile CAN1TFLGSTR _CAN1TFLG @(REG_BASE + 0x00000186);   /* MSCAN 1 Transmitter Flag Register; 0x00000186 */ 
volatile CAN1TIERSTR _CAN1TIER @(REG_BASE + 0x00000187);   /* MSCAN 1 Transmitter Interrupt Enable Register; 0x00000187 */ 
volatile CAN1TARQSTR _CAN1TARQ @(REG_BASE + 0x00000188);   /* MSCAN 1 Transmitter Message Abort Request; 0x00000188 */ 
volatile CAN1TAAKSTR _CAN1TAAK @(REG_BASE + 0x00000189);   /* MSCAN 1 Transmitter Message Abort Control; 0x00000189 */ 
volatile CAN1TBSELSTR _CAN1TBSEL @(REG_BASE + 0x0000018A); /* MSCAN 1 Transmit Buffer Selection; 0x0000018A */ 
volatile CAN1IDACSTR _CAN1IDAC @(REG_BASE + 0x0000018B);   /* MSCAN 1 Identifier Acceptance Control Register; 0x0000018B */ 
volatile CAN1RXERRSTR _CAN1RXERR @(REG_BASE + 0x0000018E); /* MSCAN 1 Receive Error Counter Register; 0x0000018E */ 
volatile CAN1TXERRSTR _CAN1TXERR @(REG_BASE + 0x0000018F); /* MSCAN 1 Transmit Error Counter Register; 0x0000018F */ 
volatile CAN1IDAR0STR _CAN1IDAR0 @(REG_BASE + 0x00000190); /* MSCAN 1 Identifier Acceptance Register 0; 0x00000190 */ 
volatile CAN1IDAR1STR _CAN1IDAR1 @(REG_BASE + 0x00000191); /* MSCAN 1 Identifier Acceptance Register 1; 0x00000191 */ 
volatile CAN1IDAR2STR _CAN1IDAR2 @(REG_BASE + 0x00000192); /* MSCAN 1 Identifier Acceptance Register 2; 0x00000192 */ 
volatile CAN1IDAR3STR _CAN1IDAR3 @(REG_BASE + 0x00000193); /* MSCAN 1 Identifier Acceptance Register 3; 0x00000193 */ 
volatile CAN1IDMR0STR _CAN1IDMR0 @(REG_BASE + 0x00000194); /* MSCAN 1 Identifier Mask Register 0; 0x00000194 */ 
volatile CAN1IDMR1STR _CAN1IDMR1 @(REG_BASE + 0x00000195); /* MSCAN 1 Identifier Mask Register 1; 0x00000195 */ 
volatile CAN1IDMR2STR _CAN1IDMR2 @(REG_BASE + 0x00000196); /* MSCAN 1 Identifier Mask Register 2; 0x00000196 */ 
volatile CAN1IDMR3STR _CAN1IDMR3 @(REG_BASE + 0x00000197); /* MSCAN 1 Identifier Mask Register 3; 0x00000197 */ 
volatile CAN1IDAR4STR _CAN1IDAR4 @(REG_BASE + 0x00000198); /* MSCAN 1 Identifier Acceptance Register 4; 0x00000198 */ 
volatile CAN1IDAR5STR _CAN1IDAR5 @(REG_BASE + 0x00000199); /* MSCAN 1 Identifier Acceptance Register 5; 0x00000199 */ 
volatile CAN1IDAR6STR _CAN1IDAR6 @(REG_BASE + 0x0000019A); /* MSCAN 1 Identifier Acceptance Register 6; 0x0000019A */ 
volatile CAN1IDAR7STR _CAN1IDAR7 @(REG_BASE + 0x0000019B); /* MSCAN 1 Identifier Acceptance Register 7; 0x0000019B */ 
volatile CAN1IDMR4STR _CAN1IDMR4 @(REG_BASE + 0x0000019C); /* MSCAN 1 Identifier Mask Register 4; 0x0000019C */ 
volatile CAN1IDMR5STR _CAN1IDMR5 @(REG_BASE + 0x0000019D); /* MSCAN 1 Identifier Mask Register 5; 0x0000019D */ 
volatile CAN1IDMR6STR _CAN1IDMR6 @(REG_BASE + 0x0000019E); /* MSCAN 1 Identifier Mask Register 6; 0x0000019E */ 
volatile CAN1IDMR7STR _CAN1IDMR7 @(REG_BASE + 0x0000019F); /* MSCAN 1 Identifier Mask Register 7; 0x0000019F */ 
volatile CAN1RXIDR0STR _CAN1RXIDR0 @(REG_BASE + 0x000001A0); /* MSCAN 1 Receive Identifier Register 0; 0x000001A0 */ 
volatile CAN1RXIDR1STR _CAN1RXIDR1 @(REG_BASE + 0x000001A1); /* MSCAN 1 Receive Identifier Register 1; 0x000001A1 */ 
volatile CAN1RXIDR2STR _CAN1RXIDR2 @(REG_BASE + 0x000001A2); /* MSCAN 1 Receive Identifier Register 2; 0x000001A2 */ 
volatile CAN1RXIDR3STR _CAN1RXIDR3 @(REG_BASE + 0x000001A3); /* MSCAN 1 Receive Identifier Register 3; 0x000001A3 */ 
volatile CAN1RXDSR0STR _CAN1RXDSR0 @(REG_BASE + 0x000001A4); /* MSCAN 1 Receive Data Segment Register 0; 0x000001A4 */ 
volatile CAN1RXDSR1STR _CAN1RXDSR1 @(REG_BASE + 0x000001A5); /* MSCAN 1 Receive Data Segment Register 1; 0x000001A5 */ 
volatile CAN1RXDSR2STR _CAN1RXDSR2 @(REG_BASE + 0x000001A6); /* MSCAN 1 Receive Data Segment Register 2; 0x000001A6 */ 
volatile CAN1RXDSR3STR _CAN1RXDSR3 @(REG_BASE + 0x000001A7); /* MSCAN 1 Receive Data Segment Register 3; 0x000001A7 */ 
volatile CAN1RXDSR4STR _CAN1RXDSR4 @(REG_BASE + 0x000001A8); /* MSCAN 1 Receive Data Segment Register 4; 0x000001A8 */ 
volatile CAN1RXDSR5STR _CAN1RXDSR5 @(REG_BASE + 0x000001A9); /* MSCAN 1 Receive Data Segment Register 5; 0x000001A9 */ 
volatile CAN1RXDSR6STR _CAN1RXDSR6 @(REG_BASE + 0x000001AA); /* MSCAN 1 Receive Data Segment Register 6; 0x000001AA */ 
volatile CAN1RXDSR7STR _CAN1RXDSR7 @(REG_BASE + 0x000001AB); /* MSCAN 1 Receive Data Segment Register 7; 0x000001AB */ 
volatile CAN1RXDLRSTR _CAN1RXDLR @(REG_BASE + 0x000001AC); /* MSCAN 1 Receive Data Length Register; 0x000001AC */ 
volatile CAN1TXIDR0STR _CAN1TXIDR0 @(REG_BASE + 0x000001B0); /* MSCAN 1 Transmit Identifier Register 0; 0x000001B0 */ 
volatile CAN1TXIDR1STR _CAN1TXIDR1 @(REG_BASE + 0x000001B1); /* MSCAN 1 Transmit Identifier Register 1; 0x000001B1 */ 
volatile CAN1TXIDR2STR _CAN1TXIDR2 @(REG_BASE + 0x000001B2); /* MSCAN 1 Transmit Identifier Register 2; 0x000001B2 */ 
volatile CAN1TXIDR3STR _CAN1TXIDR3 @(REG_BASE + 0x000001B3); /* MSCAN 1 Transmit Identifier Register 3; 0x000001B3 */ 
volatile CAN1TXDSR0STR _CAN1TXDSR0 @(REG_BASE + 0x000001B4); /* MSCAN 1 Transmit Data Segment Register 0; 0x000001B4 */ 
volatile CAN1TXDSR1STR _CAN1TXDSR1 @(REG_BASE + 0x000001B5); /* MSCAN 1 Transmit Data Segment Register 1; 0x000001B5 */ 
volatile CAN1TXDSR2STR _CAN1TXDSR2 @(REG_BASE + 0x000001B6); /* MSCAN 1 Transmit Data Segment Register 2; 0x000001B6 */ 
volatile CAN1TXDSR3STR _CAN1TXDSR3 @(REG_BASE + 0x000001B7); /* MSCAN 1 Transmit Data Segment Register 3; 0x000001B7 */ 
volatile CAN1TXDSR4STR _CAN1TXDSR4 @(REG_BASE + 0x000001B8); /* MSCAN 1 Transmit Data Segment Register 4; 0x000001B8 */ 
volatile CAN1TXDSR5STR _CAN1TXDSR5 @(REG_BASE + 0x000001B9); /* MSCAN 1 Transmit Data Segment Register 5; 0x000001B9 */ 
volatile CAN1TXDSR6STR _CAN1TXDSR6 @(REG_BASE + 0x000001BA); /* MSCAN 1 Transmit Data Segment Register 6; 0x000001BA */ 
volatile CAN1TXDSR7STR _CAN1TXDSR7 @(REG_BASE + 0x000001BB); /* MSCAN 1 Transmit Data Segment Register 7; 0x000001BB */ 
volatile CAN1TXDLRSTR _CAN1TXDLR @(REG_BASE + 0x000001BC); /* MSCAN 1 Transmit Data Length Register; 0x000001BC */ 
volatile CAN1TXTBPRSTR _CAN1TXTBPR @(REG_BASE + 0x000001BD); /* MSCAN 1 Transmit Buffer Priority; 0x000001BD */ 
volatile MCCTL0STR _MCCTL0 @(REG_BASE + 0x000001C0);       /* Motor Controller Control Register 0; 0x000001C0 */ 
volatile MCCTL1STR _MCCTL1 @(REG_BASE + 0x000001C1);       /* Motor Controller Control Register 1; 0x000001C1 */ 
volatile MCCC0STR _MCCC0 @(REG_BASE + 0x000001D0);         /* Motor Controller Control Register Channel 0; 0x000001D0 */ 
volatile MCCC1STR _MCCC1 @(REG_BASE + 0x000001D1);         /* Motor Controller Control Register Channel 1; 0x000001D1 */ 
volatile MCCC2STR _MCCC2 @(REG_BASE + 0x000001D2);         /* Motor Controller Control Register Channel 2; 0x000001D2 */ 
volatile MCCC3STR _MCCC3 @(REG_BASE + 0x000001D3);         /* Motor Controller Control Register Channel 3; 0x000001D3 */ 
volatile MCCC4STR _MCCC4 @(REG_BASE + 0x000001D4);         /* Motor Controller Control Register Channel 4; 0x000001D4 */ 
volatile MCCC5STR _MCCC5 @(REG_BASE + 0x000001D5);         /* Motor Controller Control Register Channel 5; 0x000001D5 */ 
volatile MCCC6STR _MCCC6 @(REG_BASE + 0x000001D6);         /* Motor Controller Control Register Channel 6; 0x000001D6 */ 
volatile MCCC7STR _MCCC7 @(REG_BASE + 0x000001D7);         /* Motor Controller Control Register Channel 7; 0x000001D7 */ 
volatile MCCC8STR _MCCC8 @(REG_BASE + 0x000001D8);         /* Motor Controller Control Register Channel 8; 0x000001D8 */ 
volatile MCCC9STR _MCCC9 @(REG_BASE + 0x000001D9);         /* Motor Controller Control Register Channel 9; 0x000001D9 */ 
volatile MCCC10STR _MCCC10 @(REG_BASE + 0x000001DA);       /* Motor Controller Control Register Channel 10; 0x000001DA */ 
volatile MCCC11STR _MCCC11 @(REG_BASE + 0x000001DB);       /* Motor Controller Control Register Channel 11; 0x000001DB */ 
volatile PTTSTR _PTT @(REG_BASE + 0x00000200);             /* Port T I/O Register; 0x00000200 */ 
volatile PTITSTR _PTIT @(REG_BASE + 0x00000201);           /* Port T Input Register; 0x00000201 */ 
volatile DDRTSTR _DDRT @(REG_BASE + 0x00000202);           /* Port T Data Direction Register; 0x00000202 */ 
volatile RDRTSTR _RDRT @(REG_BASE + 0x00000203);           /* Port T Reduced Drive Register; 0x00000203 */ 
volatile PERTSTR _PERT @(REG_BASE + 0x00000204);           /* Port T Pull Device Enable Register; 0x00000204 */ 
volatile PPSTSTR _PPST @(REG_BASE + 0x00000205);           /* Port T Polarity Select Register; 0x00000205 */ 
volatile PTSSTR _PTS @(REG_BASE + 0x00000208);             /* Port S I/O Register; 0x00000208 */ 
volatile PTISSTR _PTIS @(REG_BASE + 0x00000209);           /* Port S Input Register; 0x00000209 */ 
volatile DDRSSTR _DDRS @(REG_BASE + 0x0000020A);           /* Port S Data Direction Register; 0x0000020A */ 
volatile RDRSSTR _RDRS @(REG_BASE + 0x0000020B);           /* Port S Reduced Drive Register; 0x0000020B */ 
volatile PERSSTR _PERS @(REG_BASE + 0x0000020C);           /* Port S Pull Device Enable Register; 0x0000020C */ 
volatile PPSSSTR _PPSS @(REG_BASE + 0x0000020D);           /* Port S Polarity Select Register; 0x0000020D */ 
volatile WOMSSTR _WOMS @(REG_BASE + 0x0000020E);           /* Port S Wired-Or Mode Register; 0x0000020E */ 
volatile PTMSTR _PTM @(REG_BASE + 0x00000210);             /* Port M I/O Register; 0x00000210 */ 
volatile PTIMSTR _PTIM @(REG_BASE + 0x00000211);           /* Port M Input Register; 0x00000211 */ 
volatile DDRMSTR _DDRM @(REG_BASE + 0x00000212);           /* Port M Data Direction Register; 0x00000212 */ 
volatile RDRMSTR _RDRM @(REG_BASE + 0x00000213);           /* Port M Reduced Drive Register; 0x00000213 */ 
volatile PERMSTR _PERM @(REG_BASE + 0x00000214);           /* Port M Pull Device Enable Register; 0x00000214 */ 
volatile PPSMSTR _PPSM @(REG_BASE + 0x00000215);           /* Port M Polarity Select Register; 0x00000215 */ 
volatile WOMMSTR _WOMM @(REG_BASE + 0x00000216);           /* Port M Wired-Or Mode Register; 0x00000216 */ 
volatile PTPSTR _PTP @(REG_BASE + 0x00000218);             /* Port P I/O Register; 0x00000218 */ 
volatile PTIPSTR _PTIP @(REG_BASE + 0x00000219);           /* Port P Input Register; 0x00000219 */ 
volatile DDRPSTR _DDRP @(REG_BASE + 0x0000021A);           /* Port P Data Direction Register; 0x0000021A */ 
volatile RDRPSTR _RDRP @(REG_BASE + 0x0000021B);           /* Port P Reduced Drive Register; 0x0000021B */ 
volatile PERPSTR _PERP @(REG_BASE + 0x0000021C);           /* Port P Pull Device Enable Register; 0x0000021C */ 
volatile PPSPSTR _PPSP @(REG_BASE + 0x0000021D);           /* Port P Polarity Select Register; 0x0000021D */ 
volatile PTHSTR _PTH @(REG_BASE + 0x00000220);             /* Port H I/O Register; 0x00000220 */ 
volatile PTIHSTR _PTIH @(REG_BASE + 0x00000221);           /* Port H Input Register; 0x00000221 */ 
volatile DDRHSTR _DDRH @(REG_BASE + 0x00000222);           /* Port H Data Direction Register; 0x00000222 */ 
volatile RDRHSTR _RDRH @(REG_BASE + 0x00000223);           /* Port H Reduced Drive Register; 0x00000223 */ 
volatile PERHSTR _PERH @(REG_BASE + 0x00000224);           /* Port H Pull Device Enable Register; 0x00000224 */ 
volatile PPSHSTR _PPSH @(REG_BASE + 0x00000225);           /* Port H Polarity Select Register; 0x00000225 */ 
volatile PIEHSTR _PIEH @(REG_BASE + 0x00000226);           /* Port H Interrupt Enable Register; 0x00000226 */ 
volatile PIFHSTR _PIFH @(REG_BASE + 0x00000227);           /* Port H Interrupt Flag Register; 0x00000227 */ 
volatile PTJSTR _PTJ @(REG_BASE + 0x00000228);             /* Port J I/O Register; 0x00000228 */ 
volatile PTIJSTR _PTIJ @(REG_BASE + 0x00000229);           /* Port J Input Register; 0x00000229 */ 
volatile DDRJSTR _DDRJ @(REG_BASE + 0x0000022A);           /* Port J Data Direction Register; 0x0000022A */ 
volatile RDRJSTR _RDRJ @(REG_BASE + 0x0000022B);           /* Port J Reduced Drive Register; 0x0000022B */ 
volatile PERJSTR _PERJ @(REG_BASE + 0x0000022C);           /* Port J Pull Device Enable Register; 0x0000022C */ 
volatile PPSJSTR _PPSJ @(REG_BASE + 0x0000022D);           /* Port J Polarity Select Register; 0x0000022D */ 
volatile PIEJSTR _PIEJ @(REG_BASE + 0x0000022E);           /* Port J Interrupt Enable Register; 0x0000022E */ 
volatile PIFJSTR _PIFJ @(REG_BASE + 0x0000022F);           /* Port J Interrupt Flag Register; 0x0000022F */ 
volatile PTLSTR _PTL @(REG_BASE + 0x00000230);             /* Port L I/O Register; 0x00000230 */ 
volatile PTILSTR _PTIL @(REG_BASE + 0x00000231);           /* Port L Input Register; 0x00000231 */ 
volatile DDRLSTR _DDRL @(REG_BASE + 0x00000232);           /* Port L Data Direction Register; 0x00000232 */ 
volatile RDRLSTR _RDRL @(REG_BASE + 0x00000233);           /* Port L Reduced Drive Register; 0x00000233 */ 
volatile PERLSTR _PERL @(REG_BASE + 0x00000234);           /* Port L Pull Device Enable Register; 0x00000234 */ 
volatile PPSLSTR _PPSL @(REG_BASE + 0x00000235);           /* Port L Polarity Select Register; 0x00000235 */ 
volatile PTUSTR _PTU @(REG_BASE + 0x00000238);             /* Port U I/O Register; 0x00000238 */ 
volatile PTIUSTR _PTIU @(REG_BASE + 0x00000239);           /* Port U Input Register; 0x00000239 */ 
volatile DDRUSTR _DDRU @(REG_BASE + 0x0000023A);           /* Port U Data Direction Register; 0x0000023A */ 
volatile SRRUSTR _SRRU @(REG_BASE + 0x0000023B);           /* Port U Slew Rate Register; 0x0000023B */ 
volatile PERUSTR _PERU @(REG_BASE + 0x0000023C);           /* Port U Pull Device Enable Register; 0x0000023C */ 
volatile PPSUSTR _PPSU @(REG_BASE + 0x0000023D);           /* Port U Polarity Select Register; 0x0000023D */ 
volatile PTVSTR _PTV @(REG_BASE + 0x00000240);             /* Port V I/O Register; 0x00000240 */ 
volatile PTIVSTR _PTIV @(REG_BASE + 0x00000241);           /* Port V Input Register; 0x00000241 */ 
volatile DDRVSTR _DDRV @(REG_BASE + 0x00000242);           /* Port V Data Direction Register; 0x00000242 */ 
volatile SRRVSTR _SRRV @(REG_BASE + 0x00000243);           /* Port V Reduced Drive Register; 0x00000243 */ 
volatile PERVSTR _PERV @(REG_BASE + 0x00000244);           /* Port V Pull Device Enable Register; 0x00000244 */ 
volatile PPSVSTR _PPSV @(REG_BASE + 0x00000245);           /* Port V Polarity Select Register; 0x00000245 */ 
volatile PTWSTR _PTW @(REG_BASE + 0x00000248);             /* Port W I/O Register; 0x00000248 */ 
volatile PTIWSTR _PTIW @(REG_BASE + 0x00000249);           /* Port W Input Register; 0x00000249 */ 
volatile DDRWSTR _DDRW @(REG_BASE + 0x0000024A);           /* Port W Data Direction Register; 0x0000024A */ 
volatile SRRWSTR _SRRW @(REG_BASE + 0x0000024B);           /* Port W Reduced Drive Register; 0x0000024B */ 
volatile PERWSTR _PERW @(REG_BASE + 0x0000024C);           /* Port W Pull Device Enable Register; 0x0000024C */ 
volatile PPSWSTR _PPSW @(REG_BASE + 0x0000024D);           /* Port W Polarity Select Register; 0x0000024D */ 
 
 
/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */ 
volatile PORTABSTR _PORTAB @(REG_BASE + 0x00000000);       /* Port AB Register; 0x00000000 */ 
volatile DDRABSTR _DDRAB @(REG_BASE + 0x00000002);         /* Port AB Data Direction Register; 0x00000002 */ 
volatile PARTIDSTR _PARTID @(REG_BASE + 0x0000001A);       /* Part ID Register; 0x0000001A */ 
volatile TCNTSTR _TCNT @(REG_BASE + 0x00000044);           /* Timer Count Register; 0x00000044 */ 
volatile TC0STR _TC0 @(REG_BASE + 0x00000050);             /* Timer Input Capture/Output Compare Register 0; 0x00000050 */ 
volatile TC1STR _TC1 @(REG_BASE + 0x00000052);             /* Timer Input Capture/Output Compare Register 1; 0x00000052 */ 
volatile TC2STR _TC2 @(REG_BASE + 0x00000054);             /* Timer Input Capture/Output Compare Register 2; 0x00000054 */ 
volatile TC3STR _TC3 @(REG_BASE + 0x00000056);             /* Timer Input Capture/Output Compare Register 3; 0x00000056 */ 
volatile TC4STR _TC4 @(REG_BASE + 0x00000058);             /* Timer Input Capture/Output Compare Register 4; 0x00000058 */ 
volatile TC5STR _TC5 @(REG_BASE + 0x0000005A);             /* Timer Input Capture/Output Compare Register 5; 0x0000005A */ 
volatile TC6STR _TC6 @(REG_BASE + 0x0000005C);             /* Timer Input Capture/Output Compare Register 6; 0x0000005C */ 
volatile TC7STR _TC7 @(REG_BASE + 0x0000005E);             /* Timer Input Capture/Output Compare Register 7; 0x0000005E */ 
volatile PACNTSTR _PACNT @(REG_BASE + 0x00000062);         /* Pulse Accumulators Count Register; 0x00000062 */ 
volatile ATDCTL23STR _ATDCTL23 @(REG_BASE + 0x00000082);   /* ATD Control Register 23; 0x00000082 */ 
volatile ATDCTL45STR _ATDCTL45 @(REG_BASE + 0x00000084);   /* ATD Control Register 45; 0x00000084 */ 
volatile ATDDIENSTR _ATDDIEN @(REG_BASE + 0x0000008C);     /* ATD Input Enable Register; 0x0000008C */ 
volatile PORTADSTR _PORTAD @(REG_BASE + 0x0000008E);       /* Port AD0 Data; 0x0000008E */ 
volatile ATDDR0STR _ATDDR0 @(REG_BASE + 0x00000090);       /* ATD Conversion Result Register 0; 0x00000090 */ 
volatile ATDDR1STR _ATDDR1 @(REG_BASE + 0x00000092);       /* ATD Conversion Result Register 1; 0x00000092 */ 
volatile ATDDR2STR _ATDDR2 @(REG_BASE + 0x00000094);       /* ATD Conversion Result Register 2; 0x00000094 */ 
volatile ATDDR3STR _ATDDR3 @(REG_BASE + 0x00000096);       /* ATD Conversion Result Register 3; 0x00000096 */ 
volatile ATDDR4STR _ATDDR4 @(REG_BASE + 0x00000098);       /* ATD Conversion Result Register 4; 0x00000098 */ 
volatile ATDDR5STR _ATDDR5 @(REG_BASE + 0x0000009A);       /* ATD Conversion Result Register 5; 0x0000009A */ 
volatile ATDDR6STR _ATDDR6 @(REG_BASE + 0x0000009C);       /* ATD Conversion Result Register 6; 0x0000009C */ 
volatile ATDDR7STR _ATDDR7 @(REG_BASE + 0x0000009E);       /* ATD Conversion Result Register 7; 0x0000009E */ 
volatile ATDDR8STR _ATDDR8 @(REG_BASE + 0x000000A0);       /* ATD Conversion Result Register 8; 0x000000A0 */ 
volatile ATDDR9STR _ATDDR9 @(REG_BASE + 0x000000A2);       /* ATD Conversion Result Register 9; 0x000000A2 */ 
volatile ATDDR10STR _ATDDR10 @(REG_BASE + 0x000000A4);     /* ATD Conversion Result Register 10; 0x000000A4 */ 
volatile ATDDR11STR _ATDDR11 @(REG_BASE + 0x000000A6);     /* ATD Conversion Result Register 11; 0x000000A6 */ 
volatile ATDDR12STR _ATDDR12 @(REG_BASE + 0x000000A8);     /* ATD Conversion Result Register 12; 0x000000A8 */ 
volatile ATDDR13STR _ATDDR13 @(REG_BASE + 0x000000AA);     /* ATD Conversion Result Register 13; 0x000000AA */ 
volatile ATDDR14STR _ATDDR14 @(REG_BASE + 0x000000AC);     /* ATD Conversion Result Register 14; 0x000000AC */ 
volatile ATDDR15STR _ATDDR15 @(REG_BASE + 0x000000AE);     /* ATD Conversion Result Register 15; 0x000000AE */ 
volatile SCI0BDSTR _SCI0BD @(REG_BASE + 0x000000C8);       /* SCI 0 Baud Rate Register; 0x000000C8 */ 
volatile SCI1BDSTR _SCI1BD @(REG_BASE + 0x000000D0);       /* SCI 1 Baud Rate Register; 0x000000D0 */ 
volatile PWMCNT01STR _PWMCNT01 @(REG_BASE + 0x000000EC);   /* PWM Channel Counter 01 Register; 0x000000EC */ 
volatile PWMCNT23STR _PWMCNT23 @(REG_BASE + 0x000000EE);   /* PWM Channel Counter 23 Register; 0x000000EE */ 
volatile PWMCNT45STR _PWMCNT45 @(REG_BASE + 0x000000F0);   /* PWM Channel Counter 45 Register; 0x000000F0 */ 
volatile PWMPER01STR _PWMPER01 @(REG_BASE + 0x000000F2);   /* PWM Channel Period 01 Register; 0x000000F2 */ 
volatile PWMPER23STR _PWMPER23 @(REG_BASE + 0x000000F4);   /* PWM Channel Period 23 Register; 0x000000F4 */ 
volatile PWMPER45STR _PWMPER45 @(REG_BASE + 0x000000F6);   /* PWM Channel Period 45 Register; 0x000000F6 */ 
volatile PWMDTY01STR _PWMDTY01 @(REG_BASE + 0x000000F8);   /* PWM Channel Duty 01 Register; 0x000000F8 */ 
volatile PWMDTY23STR _PWMDTY23 @(REG_BASE + 0x000000FA);   /* PWM Channel Duty 23 Register; 0x000000FA */ 
volatile PWMDTY45STR _PWMDTY45 @(REG_BASE + 0x000000FC);   /* PWM Channel Duty 45 Register; 0x000000FC */ 
volatile CAN0RXTSRSTR _CAN0RXTSR @(REG_BASE + 0x0000016E); /* MSCAN 0 Receive Time Stamp Register; 0x0000016E */ 
volatile CAN0TXTSRSTR _CAN0TXTSR @(REG_BASE + 0x0000017E); /* MSCAN 0 Transmit Time Stamp Register; 0x0000017E */ 
volatile CAN1RXTSRSTR _CAN1RXTSR @(REG_BASE + 0x000001AE); /* MSCAN 1 Receive Time Stamp Register; 0x000001AE */ 
volatile CAN1TXTSRSTR _CAN1TXTSR @(REG_BASE + 0x000001BE); /* MSCAN 1 Transmit Time Stamp Register; 0x000001BE */ 
volatile MCPERSTR _MCPER @(REG_BASE + 0x000001C2);         /* Motor Controller Period Register, with DITH = 0; 0x000001C2 */ 
volatile MCDC0STR _MCDC0 @(REG_BASE + 0x000001E0);         /* Motor Controller Duty Cycle Register 0; 0x000001E0 */ 
volatile MCDC1STR _MCDC1 @(REG_BASE + 0x000001E2);         /* Motor Controller Duty Cycle Register 1; 0x000001E2 */ 
volatile MCDC2STR _MCDC2 @(REG_BASE + 0x000001E4);         /* Motor Controller Duty Cycle Register 2; 0x000001E4 */ 
volatile MCDC3STR _MCDC3 @(REG_BASE + 0x000001E6);         /* Motor Controller Duty Cycle Register 3; 0x000001E6 */ 
volatile MCDC4STR _MCDC4 @(REG_BASE + 0x000001E8);         /* Motor Controller Duty Cycle Register 4; 0x000001E8 */ 
volatile MCDC5STR _MCDC5 @(REG_BASE + 0x000001EA);         /* Motor Controller Duty Cycle Register 5; 0x000001EA */ 
volatile MCDC6STR _MCDC6 @(REG_BASE + 0x000001EC);         /* Motor Controller Duty Cycle Register 6; 0x000001EC */ 
volatile MCDC7STR _MCDC7 @(REG_BASE + 0x000001EE);         /* Motor Controller Duty Cycle Register 7; 0x000001EE */ 
volatile MCDC8STR _MCDC8 @(REG_BASE + 0x000001F0);         /* Motor Controller Duty Cycle Register 8; 0x000001F0 */ 
volatile MCDC9STR _MCDC9 @(REG_BASE + 0x000001F2);         /* Motor Controller Duty Cycle Register 9; 0x000001F2 */ 
volatile MCDC10STR _MCDC10 @(REG_BASE + 0x000001F4);       /* Motor Controller Duty Cycle Register 10; 0x000001F4 */ 
volatile MCDC11STR _MCDC11 @(REG_BASE + 0x000001F6);       /* Motor Controller Duty Cycle Register 11; 0x000001F6 */ 
 
/* EOF */ 
/* 
** ################################################################### 
** 
**     This file was created by UNIS Processor Expert 2.95 [03.62] 
**     for the Freescale HCS12 series of microcontrollers. 
** 
** ################################################################### 
*/