www.pudn.com > hamin0132.rar > _primary.vhd

library verilog;
use verilog.vl_types.all;
entity hamgen is
    port(
        data_in         : in     vl_logic_vector(7 downto 0);
        ham_out         : out    vl_logic_vector(3 downto 0)
    );
end hamgen;