www.pudn.com > LPC1768_SD_Test.rar > system_lpc17xx.txt, change:2010-06-05,size:15317b


; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision 
; commandline ArmCC [--debug -c --asm --interleave -o.\Obj\system_lpc17xx.o --depend=.\Obj\system_lpc17xx.d --device=DARMP1 --apcs=interwork -O0 -IC:\Keil\ARM\INC\NXP --omf_browse=.\Obj\system_lpc17xx.crf system_LPC17xx.c] 
                          THUMB 
 
                          AREA ||.text||, CODE, READONLY, ALIGN=2 
 
                  SystemInit PROC 
;;;408     */ 
;;;409    void SystemInit (void) 
000000  2020              MOVS     r0,#0x20 
;;;410    { 
;;;411    #if (CLOCK_SETUP)                       /* Clock Setup                        */ 
;;;412      LPC_SC->SCS       = SCS_Val; 
000002  4970              LDR      r1,|L1.452| 
000004  6008              STR      r0,[r1,#0] 
;;;413      if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */ 
;;;414        while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */ 
000006  bf00              NOP       
                  |L1.8| 
000008  486e              LDR      r0,|L1.452| 
00000a  6800              LDR      r0,[r0,#0] 
00000c  f0100f40          TST      r0,#0x40 
000010  d0fa              BEQ      |L1.8| 
;;;415      } 
;;;416     
;;;417      LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */ 
000012  2003              MOVS     r0,#3 
000014  496b              LDR      r1,|L1.452| 
000016  399c              SUBS     r1,r1,#0x9c 
000018  6008              STR      r0,[r1,#0] 
;;;418     
;;;419    #if (PLL0_SETUP) 
;;;420      LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */ 
00001a  2001              MOVS     r0,#1 
00001c  496a              LDR      r1,|L1.456| 
00001e  f8c1010c          STR      r0,[r1,#0x10c] 
;;;421      LPC_SC->PLL0CFG   = PLL0CFG_Val; 
000022  200b              MOVS     r0,#0xb 
000024  4968              LDR      r1,|L1.456| 
000026  3184              ADDS     r1,r1,#0x84 
000028  6008              STR      r0,[r1,#0] 
;;;422      LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */ 
00002a  2001              MOVS     r0,#1 
00002c  1f09              SUBS     r1,r1,#4 
00002e  6008              STR      r0,[r1,#0] 
;;;423      LPC_SC->PLL0FEED  = 0xAA; 
000030  20aa              MOVS     r0,#0xaa 
000032  4965              LDR      r1,|L1.456| 
000034  318c              ADDS     r1,r1,#0x8c 
000036  6008              STR      r0,[r1,#0] 
;;;424      LPC_SC->PLL0FEED  = 0x55; 
000038  2055              MOVS     r0,#0x55 
00003a  4963              LDR      r1,|L1.456| 
00003c  f8c1008c          STR      r0,[r1,#0x8c] 
;;;425      while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */ 
000040  bf00              NOP       
                  |L1.66| 
000042  4861              LDR      r0,|L1.456| 
000044  3088              ADDS     r0,r0,#0x88 
000046  6800              LDR      r0,[r0,#0] 
000048  f0106f80          TST      r0,#0x4000000 
00004c  d0f9              BEQ      |L1.66| 
;;;426     
;;;427      LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */ 
00004e  2003              MOVS     r0,#3 
000050  495d              LDR      r1,|L1.456| 
000052  3180              ADDS     r1,r1,#0x80 
000054  6008              STR      r0,[r1,#0] 
;;;428      LPC_SC->PLL0FEED  = 0xAA; 
000056  20aa              MOVS     r0,#0xaa 
000058  495b              LDR      r1,|L1.456| 
00005a  f8c1008c          STR      r0,[r1,#0x8c] 
;;;429      LPC_SC->PLL0FEED  = 0x55; 
00005e  2055              MOVS     r0,#0x55 
000060  4959              LDR      r1,|L1.456| 
000062  318c              ADDS     r1,r1,#0x8c 
000064  6008              STR      r0,[r1,#0] 
;;;430    #endif 
;;;431     
;;;432    #if (PLL1_SETUP) 
;;;433      LPC_SC->PLL1CFG   = PLL1CFG_Val; 
;;;434      LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */ 
;;;435      LPC_SC->PLL1FEED  = 0xAA; 
;;;436      LPC_SC->PLL1FEED  = 0x55; 
;;;437      while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */ 
;;;438     
;;;439      LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */ 
;;;440      LPC_SC->PLL1FEED  = 0xAA; 
;;;441      LPC_SC->PLL1FEED  = 0x55; 
;;;442    #else 
;;;443      LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */ 
000066  2000              MOVS     r0,#0 
000068  4956              LDR      r1,|L1.452| 
00006a  3998              SUBS     r1,r1,#0x98 
00006c  6008              STR      r0,[r1,#0] 
;;;444    #endif 
;;;445     
;;;446      LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */ 
00006e  4955              LDR      r1,|L1.452| 
000070  3108              ADDS     r1,r1,#8 
000072  6008              STR      r0,[r1,#0] 
;;;447      LPC_SC->PCLKSEL1  = PCLKSEL1_Val; 
000074  1d09              ADDS     r1,r1,#4 
000076  6008              STR      r0,[r1,#0] 
;;;448     
;;;449      LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */ 
000078  4854              LDR      r0,|L1.460| 
00007a  4953              LDR      r1,|L1.456| 
00007c  31c4              ADDS     r1,r1,#0xc4 
00007e  6008              STR      r0,[r1,#0] 
;;;450     
;;;451      LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */ 
000080  2000              MOVS     r0,#0 
000082  4951              LDR      r1,|L1.456| 
000084  f8c101c8          STR      r0,[r1,#0x1c8] 
;;;452    #endif 
;;;453     
;;;454      /* Determine clock frequency according to clock register values             */ 
;;;455      if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected      */ 
000088  484f              LDR      r0,|L1.456| 
00008a  3088              ADDS     r0,r0,#0x88 
00008c  6800              LDR      r0,[r0,#0] 
00008e  f3c06001          UBFX     r0,r0,#24,#2 
000092  2803              CMP      r0,#3 
000094  d160              BNE      |L1.344| 
;;;456        switch (LPC_SC->CLKSRCSEL & 0x03) { 
000096  484b              LDR      r0,|L1.452| 
000098  3894              SUBS     r0,r0,#0x94 
00009a  6800              LDR      r0,[r0,#0] 
00009c  f0100003          ANDS     r0,r0,#3 
0000a0  d006              BEQ      |L1.176| 
0000a2  2801              CMP      r0,#1 
0000a4  d020              BEQ      |L1.232| 
0000a6  2802              CMP      r0,#2 
0000a8  d039              BEQ      |L1.286| 
0000aa  2803              CMP      r0,#3 
0000ac  d153              BNE      |L1.342| 
0000ae  e000              B        |L1.178| 
                  |L1.176| 
;;;457          case 0:                           /* Internal RC oscillator => PLL0     */ 
;;;458          case 3:                           /* Reserved, default to Internal RC   */ 
0000b0  bf00              NOP       
                  |L1.178| 
;;;459            SystemFrequency = (IRC_OSC *  
0000b2  4845              LDR      r0,|L1.456| 
0000b4  3088              ADDS     r0,r0,#0x88 
0000b6  6800              LDR      r0,[r0,#0] 
0000b8  f3c0000e          UBFX     r0,r0,#0,#15 
0000bc  1c40              ADDS     r0,r0,#1 
0000be  0041              LSLS     r1,r0,#1 
0000c0  4841              LDR      r0,|L1.456| 
0000c2  f8d00088          LDR      r0,[r0,#0x88] 
0000c6  f3c04007          UBFX     r0,r0,#16,#8 
0000ca  1c40              ADDS     r0,r0,#1 
0000cc  fbb1f1f0          UDIV     r1,r1,r0 
0000d0  483f              LDR      r0,|L1.464| 
0000d2  4341              MULS     r1,r0,r1 
0000d4  483b              LDR      r0,|L1.452| 
0000d6  389c              SUBS     r0,r0,#0x9c 
0000d8  6800              LDR      r0,[r0,#0] 
0000da  b2c0              UXTB     r0,r0 
0000dc  1c40              ADDS     r0,r0,#1 
0000de  fbb1f0f0          UDIV     r0,r1,r0 
0000e2  493c              LDR      r1,|L1.468| 
0000e4  6008              STR      r0,[r1,#0]  ; SystemFrequency 
;;;460                              (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 
;;;461                              (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   / 
;;;462                              ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 
;;;463            break; 
0000e6  e036              B        |L1.342| 
                  |L1.232| 
;;;464          case 1:                           /* Main oscillator => PLL0            */ 
;;;465            SystemFrequency = (OSC_CLK *  
0000e8  4837              LDR      r0,|L1.456| 
0000ea  3088              ADDS     r0,r0,#0x88 
0000ec  6800              LDR      r0,[r0,#0] 
0000ee  f3c0000e          UBFX     r0,r0,#0,#15 
0000f2  1c40              ADDS     r0,r0,#1 
0000f4  0041              LSLS     r1,r0,#1 
0000f6  4834              LDR      r0,|L1.456| 
0000f8  f8d00088          LDR      r0,[r0,#0x88] 
0000fc  f3c04007          UBFX     r0,r0,#16,#8 
000100  1c40              ADDS     r0,r0,#1 
000102  fbb1f1f0          UDIV     r1,r1,r0 
000106  4834              LDR      r0,|L1.472| 
000108  4341              MULS     r1,r0,r1 
00010a  482e              LDR      r0,|L1.452| 
00010c  389c              SUBS     r0,r0,#0x9c 
00010e  6800              LDR      r0,[r0,#0] 
000110  b2c0              UXTB     r0,r0 
000112  1c40              ADDS     r0,r0,#1 
000114  fbb1f0f0          UDIV     r0,r1,r0 
000118  492e              LDR      r1,|L1.468| 
00011a  6008              STR      r0,[r1,#0]  ; SystemFrequency 
;;;466                              (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 
;;;467                              (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   / 
;;;468                              ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 
;;;469            break; 
00011c  e01b              B        |L1.342| 
                  |L1.286| 
;;;470          case 2:                           /* RTC oscillator => PLL0             */ 
;;;471            SystemFrequency = (RTC_CLK *  
00011e  482a              LDR      r0,|L1.456| 
000120  3088              ADDS     r0,r0,#0x88 
000122  6800              LDR      r0,[r0,#0] 
000124  f3c0000e          UBFX     r0,r0,#0,#15 
000128  1c40              ADDS     r0,r0,#1 
00012a  0041              LSLS     r1,r0,#1 
00012c  4826              LDR      r0,|L1.456| 
00012e  f8d00088          LDR      r0,[r0,#0x88] 
000132  f3c04007          UBFX     r0,r0,#16,#8 
000136  1c40              ADDS     r0,r0,#1 
000138  fbb1f1f0          UDIV     r1,r1,r0 
00013c  f44f40fa          MOV      r0,#0x7d00 
000140  4341              MULS     r1,r0,r1 
000142  4820              LDR      r0,|L1.452| 
000144  389c              SUBS     r0,r0,#0x9c 
000146  6800              LDR      r0,[r0,#0] 
000148  b2c0              UXTB     r0,r0 
00014a  1c40              ADDS     r0,r0,#1 
00014c  fbb1f0f0          UDIV     r0,r1,r0 
000150  4920              LDR      r1,|L1.468| 
000152  6008              STR      r0,[r1,#0]  ; SystemFrequency 
;;;472                              (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 
;;;473                              (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1))   / 
;;;474                              ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 
;;;475            break; 
000154  bf00              NOP       
                  |L1.342| 
000156  e030              B        |L1.442| 
                  |L1.344| 
;;;476        } 
;;;477      } else { 
;;;478        switch (LPC_SC->CLKSRCSEL & 0x03) { 
000158  481a              LDR      r0,|L1.452| 
00015a  3894              SUBS     r0,r0,#0x94 
00015c  6800              LDR      r0,[r0,#0] 
00015e  f0100003          ANDS     r0,r0,#3 
000162  d006              BEQ      |L1.370| 
000164  2801              CMP      r0,#1 
000166  d010              BEQ      |L1.394| 
000168  2802              CMP      r0,#2 
00016a  d019              BEQ      |L1.416| 
00016c  2803              CMP      r0,#3 
00016e  d123              BNE      |L1.440| 
000170  e000              B        |L1.372| 
                  |L1.370| 
;;;479          case 0:                           /* Internal RC oscillator => PLL0     */ 
;;;480          case 3:                           /* Reserved, default to Internal RC   */ 
000172  bf00              NOP       
                  |L1.372| 
;;;481            SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 
000174  4813              LDR      r0,|L1.452| 
000176  389c              SUBS     r0,r0,#0x9c 
000178  6800              LDR      r0,[r0,#0] 
00017a  b2c0              UXTB     r0,r0 
00017c  1c40              ADDS     r0,r0,#1 
00017e  4914              LDR      r1,|L1.464| 
000180  fbb1f0f0          UDIV     r0,r1,r0 
000184  4913              LDR      r1,|L1.468| 
000186  6008              STR      r0,[r1,#0]  ; SystemFrequency 
;;;482            break; 
000188  e016              B        |L1.440| 
                  |L1.394| 
;;;483          case 1:                           /* Main oscillator => PLL0            */ 
;;;484            SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 
00018a  480e              LDR      r0,|L1.452| 
00018c  389c              SUBS     r0,r0,#0x9c 
00018e  6800              LDR      r0,[r0,#0] 
000190  b2c0              UXTB     r0,r0 
000192  1c40              ADDS     r0,r0,#1 
000194  4910              LDR      r1,|L1.472| 
000196  fbb1f0f0          UDIV     r0,r1,r0 
00019a  490e              LDR      r1,|L1.468| 
00019c  6008              STR      r0,[r1,#0]  ; SystemFrequency 
;;;485            break; 
00019e  e00b              B        |L1.440| 
                  |L1.416| 
;;;486          case 2:                           /* RTC oscillator => PLL0             */ 
;;;487            SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 
0001a0  4808              LDR      r0,|L1.452| 
0001a2  389c              SUBS     r0,r0,#0x9c 
0001a4  6800              LDR      r0,[r0,#0] 
0001a6  b2c0              UXTB     r0,r0 
0001a8  1c40              ADDS     r0,r0,#1 
0001aa  f44f41fa          MOV      r1,#0x7d00 
0001ae  fbb1f0f0          UDIV     r0,r1,r0 
0001b2  4908              LDR      r1,|L1.468| 
0001b4  6008              STR      r0,[r1,#0]  ; SystemFrequency 
;;;488            break; 
0001b6  bf00              NOP       
                  |L1.440| 
0001b8  bf00              NOP                            ;482 
                  |L1.442| 
;;;489        } 
;;;490      } 
;;;491     
;;;492    #if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */ 
;;;493      LPC_SC->FLASHCFG  = FLASHCFG_Val; 
0001ba  f243003a          MOV      r0,#0x303a 
0001be  4902              LDR      r1,|L1.456| 
0001c0  6008              STR      r0,[r1,#0] 
;;;494    #endif 
;;;495    } 
0001c2  4770              BX       lr 
                          ENDP 
 
                  |L1.452| 
                          DCD      0x400fc1a0 
                  |L1.456| 
                          DCD      0x400fc000 
                  |L1.460| 
                          DCD      0x042887de 
                  |L1.464| 
                          DCD      0x003d0900 
                  |L1.468| 
                          DCD      SystemFrequency 
                  |L1.472| 
                          DCD      0x00b71b00 
 
                          AREA ||.data||, DATA, ALIGN=2 
 
                  SystemFrequency 
                          DCD      0x003d0900