www.pudn.com > LPC1768_SD_Test.rar > spi_lpc17xx.txt, change:2010-06-05,size:8286b


; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision 
; commandline ArmCC [--debug -c --asm --interleave -o.\Obj\spi_lpc17xx.o --depend=.\Obj\spi_lpc17xx.d --device=DARMP1 --apcs=interwork -O0 -IC:\Keil\ARM\INC\NXP --omf_browse=.\Obj\spi_lpc17xx.crf SPI_LPC17xx.c] 
                          THUMB 
 
                          AREA ||.text||, CODE, READONLY, ALIGN=2 
 
                  spi_init PROC 
;;;34      
;;;35     void spi_init (void) { 
000000  4836              LDR      r0,|L1.220| 
;;;36        /* Initialize and enable the SSP Interface module. */ 
;;;37      
;;;38       LPC_SC->PCONP        |= (1 << 21);          /* Enable power to SSPI0 block  */ 
000002  6800              LDR      r0,[r0,#0] 
000004  f4401000          ORR      r0,r0,#0x200000 
000008  4934              LDR      r1,|L1.220| 
00000a  39c4              SUBS     r1,r1,#0xc4 
00000c  f8c100c4          STR      r0,[r1,#0xc4] 
;;;39      
;;;40       /* SSEL is GPIO, output set to high. */ 
;;;41       LPC_GPIO0->FIODIR  |=  (1<<16);             /* P0.16 is output */ 
000010  4833              LDR      r0,|L1.224| 
000012  6800              LDR      r0,[r0,#0] 
000014  f4403080          ORR      r0,r0,#0x10000 
000018  4931              LDR      r1,|L1.224| 
00001a  6008              STR      r0,[r1,#0] 
;;;42       LPC_GPIO0->FIOPIN  |=  (1<<16);             /* set P0.16 high (SSEL inactiv) */ 
00001c  4608              MOV      r0,r1 
00001e  6940              LDR      r0,[r0,#0x14] 
000020  f4403080          ORR      r0,r0,#0x10000 
000024  6148              STR      r0,[r1,#0x14] 
;;;43       LPC_PINCON->PINSEL1 &= ~(3<<0);             /* P0.16 SSEL (used as GPIO) */ 
000026  482f              LDR      r0,|L1.228| 
000028  6840              LDR      r0,[r0,#4] 
00002a  f0200003          BIC      r0,r0,#3 
00002e  492d              LDR      r1,|L1.228| 
000030  6048              STR      r0,[r1,#4] 
;;;44      
;;;45       /* SCK, MISO, MOSI are SSP pins. */ 
;;;46       LPC_PINCON->PINSEL0 &= ~(3UL<<30);          /* P0.15 cleared */ 
000032  4608              MOV      r0,r1 
000034  6800              LDR      r0,[r0,#0] 
000036  f0204040          BIC      r0,r0,#0xc0000000 
00003a  6008              STR      r0,[r1,#0] 
;;;47       LPC_PINCON->PINSEL0 |=  (2UL<<30);          /* P0.15 SCK0 */ 
00003c  4608              MOV      r0,r1 
00003e  6800              LDR      r0,[r0,#0] 
000040  f0404000          ORR      r0,r0,#0x80000000 
000044  6008              STR      r0,[r1,#0] 
;;;48       LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));  /* P0.17, P0.18 cleared */ 
000046  4608              MOV      r0,r1 
000048  6840              LDR      r0,[r0,#4] 
00004a  f020003c          BIC      r0,r0,#0x3c 
00004e  6048              STR      r0,[r1,#4] 
;;;49       LPC_PINCON->PINSEL1 |=  ((2<<2) | (2<<4));  /* P0.17 MISO0, P0.18 MOSI0 */ 
000050  4608              MOV      r0,r1 
000052  6840              LDR      r0,[r0,#4] 
000054  f0400028          ORR      r0,r0,#0x28 
000058  6048              STR      r0,[r1,#4] 
;;;50      
;;;51       LPC_SC->PCLKSEL1 &= ~(3<<10);               /* PCLKSP0 = CCLK/4 (18MHz) */ 
00005a  4820              LDR      r0,|L1.220| 
00005c  38c4              SUBS     r0,r0,#0xc4 
00005e  f8d001ac          LDR      r0,[r0,#0x1ac] 
000062  f4206040          BIC      r0,r0,#0xc00 
000066  491d              LDR      r1,|L1.220| 
000068  39c4              SUBS     r1,r1,#0xc4 
00006a  f8c101ac          STR      r0,[r1,#0x1ac] 
;;;52       LPC_SC->PCLKSEL1 |=  (1<<10);               /* PCLKSP0 = CCLK   (72MHz) */ 
00006e  4608              MOV      r0,r1 
000070  f8d001ac          LDR      r0,[r0,#0x1ac] 
000074  f4406080          ORR      r0,r0,#0x400 
000078  4918              LDR      r1,|L1.220| 
00007a  31e8              ADDS     r1,r1,#0xe8 
00007c  6008              STR      r0,[r1,#0] 
;;;53      
;;;54       LPC_SSP0->CPSR = 180;                       /* 72MHz / 180 = 400kBit */ 
00007e  20b4              MOVS     r0,#0xb4 
000080  4919              LDR      r1,|L1.232| 
000082  6108              STR      r0,[r1,#0x10] 
;;;55                                                   /* maximum of 18MHz is possible */     
;;;56       LPC_SSP0->CR0  = 0x0007;                    /* 8Bit, CPOL=0, CPHA=0         */ 
000084  2007              MOVS     r0,#7 
000086  6008              STR      r0,[r1,#0] 
;;;57       LPC_SSP0->CR1  = 0x0002;                    /* SSP0 enable, master          */ 
000088  2002              MOVS     r0,#2 
00008a  6048              STR      r0,[r1,#4] 
;;;58     } 
00008c  4770              BX       lr 
;;;59      
                          ENDP 
 
                  spi_hi_speed PROC 
;;;62      
;;;63     void spi_hi_speed (BOOL on) { 
00008e  2801              CMP      r0,#1 
;;;64        /* Set a SPI clock speed to desired value. */ 
;;;65      
;;;66        if (on == __TRUE) { 
000090  d103              BNE      |L1.154| 
;;;67           /* Max. 12 MBit used for Data Transfer. */ 
;;;68         LPC_SSP0->CPSR =   6;                     /* 72MHz / 6   = 12MBit */ 
000092  2106              MOVS     r1,#6 
000094  4a14              LDR      r2,|L1.232| 
000096  6111              STR      r1,[r2,#0x10] 
000098  e002              B        |L1.160| 
                  |L1.154| 
;;;69        } 
;;;70        else { 
;;;71           /* Max. 400 kBit used in Card Initialization. */ 
;;;72         LPC_SSP0->CPSR = 180;                     /* 72MHz / 180 = 400kBit */ 
00009a  21b4              MOVS     r1,#0xb4 
00009c  4a12              LDR      r2,|L1.232| 
00009e  6111              STR      r1,[r2,#0x10] 
                  |L1.160| 
;;;73        } 
;;;74     } 
0000a0  4770              BX       lr 
;;;75      
                          ENDP 
 
                  spi_ss PROC 
;;;78      
;;;79     void spi_ss (U32 ss) { 
0000a2  b130              CBZ      r0,|L1.178| 
;;;80        /* Enable/Disable SPI Chip Select (drive it high or low). */ 
;;;81      
;;;82       if (ss) { 
;;;83         LPC_GPIO0->FIOPIN |= (1<<16);             /* SSEL is GPIO, output set to high. */ 
0000a4  490e              LDR      r1,|L1.224| 
0000a6  6949              LDR      r1,[r1,#0x14] 
0000a8  f4413180          ORR      r1,r1,#0x10000 
0000ac  4a0c              LDR      r2,|L1.224| 
0000ae  6151              STR      r1,[r2,#0x14] 
0000b0  e005              B        |L1.190| 
                  |L1.178| 
;;;84       } else { 
;;;85         LPC_GPIO0->FIOPIN &= ~(1<<16);            /* SSEL is GPIO, output set to high. */ 
0000b2  490b              LDR      r1,|L1.224| 
0000b4  6949              LDR      r1,[r1,#0x14] 
0000b6  f4213180          BIC      r1,r1,#0x10000 
0000ba  4a09              LDR      r2,|L1.224| 
0000bc  6151              STR      r1,[r2,#0x14] 
                  |L1.190| 
;;;86       } 
;;;87     } 
0000be  4770              BX       lr 
;;;88      
                          ENDP 
 
                  spi_send PROC 
;;;91      
;;;92     U8 spi_send (U8 outb) { 
0000c0  4601              MOV      r1,r0 
;;;93        /* Write and Read a byte on SPI interface. */ 
;;;94      
;;;95       LPC_SSP0->DR = outb; 
0000c2  4809              LDR      r0,|L1.232| 
0000c4  6081              STR      r1,[r0,#8] 
;;;96       while (LPC_SSP0->SR & BSY);                 /* Wait for transfer to finish */ 
0000c6  bf00              NOP       
                  |L1.200| 
0000c8  4807              LDR      r0,|L1.232| 
0000ca  68c0              LDR      r0,[r0,#0xc] 
0000cc  f0100f10          TST      r0,#0x10 
0000d0  d1fa              BNE      |L1.200| 
;;;97       return (LPC_SSP0->DR);                      /* Return received value */ 
0000d2  4805              LDR      r0,|L1.232| 
0000d4  6880              LDR      r0,[r0,#8] 
0000d6  b2c0              UXTB     r0,r0 
;;;98      
;;;99     } 
0000d8  4770              BX       lr 
;;;100     
                          ENDP 
 
0000da  0000              DCW      0x0000 
                  |L1.220| 
                          DCD      0x400fc0c4 
                  |L1.224| 
                          DCD      0x2009c000 
                  |L1.228| 
                          DCD      0x4002c000 
                  |L1.232| 
                          DCD      0x40088000