www.pudn.com > LPC1768_SD_Test.rar > serial.i, change:2010-06-05,size:39612b


#line 1 "Serial.c" 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
#line 1 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
  
 
typedef enum IRQn 
{ 
  
  NonMaskableInt_IRQn           = -14,        
  MemoryManagement_IRQn         = -12,        
  BusFault_IRQn                 = -11,        
  UsageFault_IRQn               = -10,        
  SVCall_IRQn                   = -5,         
  DebugMonitor_IRQn             = -4,         
  PendSV_IRQn                   = -2,         
  SysTick_IRQn                  = -1,         
 
  
  WDT_IRQn                      = 0,          
  TIMER0_IRQn                   = 1,          
  TIMER1_IRQn                   = 2,          
  TIMER2_IRQn                   = 3,          
  TIMER3_IRQn                   = 4,          
  UART0_IRQn                    = 5,          
  UART1_IRQn                    = 6,          
  UART2_IRQn                    = 7,          
  UART3_IRQn                    = 8,          
  PWM1_IRQn                     = 9,          
  I2C0_IRQn                     = 10,         
  I2C1_IRQn                     = 11,         
  I2C2_IRQn                     = 12,         
  SPI_IRQn                      = 13,         
  SSP0_IRQn                     = 14,         
  SSP1_IRQn                     = 15,         
  PLL0_IRQn                     = 16,         
  RTC_IRQn                      = 17,         
  EINT0_IRQn                    = 18,         
  EINT1_IRQn                    = 19,         
  EINT2_IRQn                    = 20,         
  EINT3_IRQn                    = 21,         
  ADC_IRQn                      = 22,         
  BOD_IRQn                      = 23,         
  USB_IRQn                      = 24,         
  CAN_IRQn                      = 25,         
  DMA_IRQn                      = 26,         
  I2S_IRQn                      = 27,         
  ENET_IRQn                     = 28,         
  RIT_IRQn                      = 29,         
  MCPWM_IRQn                    = 30,         
  QEI_IRQn                      = 31,         
  PLL1_IRQn                     = 32,         
} IRQn_Type; 
 
 
 
 
 
 
  
 
  
 
 
 
 
 
#line 1 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
  
  
  
  
  
  
  
  
 
 
#line 1 "C:\\Keil\\\\ARM\\RV31\\INC\\stdint.h" 
  
  
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
#line 25 "C:\\Keil\\\\ARM\\RV31\\INC\\stdint.h" 
 
 
 
 
 
 
 
  
 
      
 
      
typedef   signed          char int8_t; 
typedef   signed short     int int16_t; 
typedef   signed           int int32_t; 
typedef   signed       __int64 int64_t; 
 
      
typedef unsigned          char uint8_t; 
typedef unsigned short     int uint16_t; 
typedef unsigned           int uint32_t; 
typedef unsigned       __int64 uint64_t; 
 
      
 
      
      
typedef   signed          char int_least8_t; 
typedef   signed short     int int_least16_t; 
typedef   signed           int int_least32_t; 
typedef   signed       __int64 int_least64_t; 
 
      
typedef unsigned          char uint_least8_t; 
typedef unsigned short     int uint_least16_t; 
typedef unsigned           int uint_least32_t; 
typedef unsigned       __int64 uint_least64_t; 
 
      
 
      
typedef   signed           int int_fast8_t; 
typedef   signed           int int_fast16_t; 
typedef   signed           int int_fast32_t; 
typedef   signed       __int64 int_fast64_t; 
 
      
typedef unsigned           int uint_fast8_t; 
typedef unsigned           int uint_fast16_t; 
typedef unsigned           int uint_fast32_t; 
typedef unsigned       __int64 uint_fast64_t; 
 
      
typedef   signed           int intptr_t; 
typedef unsigned           int uintptr_t; 
 
      
typedef   signed       __int64 intmax_t; 
typedef unsigned       __int64 uintmax_t; 
 
 
 
 
      
 
      
 
 
 
 
 
      
 
 
 
 
 
      
 
 
 
 
 
      
 
      
 
 
 
 
 
      
 
 
 
 
 
      
 
 
 
 
 
      
 
      
 
 
 
 
 
      
 
 
 
 
 
      
 
 
 
 
 
      
 
      
 
 
      
 
 
      
 
 
      
 
      
 
 
      
 
 
      
 
 
      
 
      
 
 
 
      
 
 
 
      
 
 
      
     
  
 
 
 
#line 196 "C:\\Keil\\\\ARM\\RV31\\INC\\stdint.h" 
 
      
 
 
 
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
      
 
 
 
 
 
 
 
 
 
 
 
#line 260 "C:\\Keil\\\\ARM\\RV31\\INC\\stdint.h" 
 
 
 
  
 
 
#line 86 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
#line 112 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
 
 
 
  
 
 
  
 
 
 
 
 
  
 
 
 
 
 
 
  
typedef struct 
{ 
  volatile uint32_t ISER[8];                        
       uint32_t RESERVED0[24]; 
  volatile uint32_t ICER[8];                        
       uint32_t RSERVED1[24]; 
  volatile uint32_t ISPR[8];                        
       uint32_t RESERVED2[24]; 
  volatile uint32_t ICPR[8];                        
       uint32_t RESERVED3[24]; 
  volatile uint32_t IABR[8];                        
       uint32_t RESERVED4[56]; 
  volatile uint8_t  IP[240];                        
       uint32_t RESERVED5[644]; 
  volatile  uint32_t STIR;                           
}  NVIC_Type; 
 
 
  
typedef struct 
{ 
  volatile const  uint32_t CPUID;                          
  volatile uint32_t ICSR;                           
  volatile uint32_t VTOR;                           
  volatile uint32_t AIRCR;                          
  volatile uint32_t SCR;                            
  volatile uint32_t CCR;                            
  volatile uint8_t  SHP[12];                        
  volatile uint32_t SHCSR;                          
  volatile uint32_t CFSR;                           
  volatile uint32_t HFSR;                           
  volatile uint32_t DFSR;                           
  volatile uint32_t MMFAR;                          
  volatile uint32_t BFAR;                           
  volatile uint32_t AFSR;                           
  volatile const  uint32_t PFR[2];                         
  volatile const  uint32_t DFR;                            
  volatile const  uint32_t ADR;                            
  volatile const  uint32_t MMFR[4];                        
  volatile const  uint32_t ISAR[5];                        
} SCB_Type; 
 
 
  
typedef struct 
{ 
  volatile uint32_t CTRL;                           
  volatile uint32_t LOAD;                           
  volatile uint32_t VAL;                            
  volatile const  uint32_t CALIB;                          
} SysTick_Type; 
 
 
  
typedef struct 
{ 
  volatile  union   
  { 
    volatile  uint8_t    u8;                         
    volatile  uint16_t   u16;                        
    volatile  uint32_t   u32;                        
  }  PORT [32];                                 
       uint32_t RESERVED0[864]; 
  volatile uint32_t TER;                            
       uint32_t RESERVED1[15]; 
  volatile uint32_t TPR;                            
       uint32_t RESERVED2[15]; 
  volatile uint32_t TCR;                            
       uint32_t RESERVED3[29]; 
  volatile uint32_t IWR;                            
  volatile uint32_t IRR;                            
  volatile uint32_t IMCR;                           
       uint32_t RESERVED4[43]; 
  volatile uint32_t LAR;                            
  volatile uint32_t LSR;                            
       uint32_t RESERVED5[6]; 
  volatile const  uint32_t PID4;                           
  volatile const  uint32_t PID5; 
  volatile const  uint32_t PID6; 
  volatile const  uint32_t PID7; 
  volatile const  uint32_t PID0; 
  volatile const  uint32_t PID1; 
  volatile const  uint32_t PID2; 
  volatile const  uint32_t PID3; 
  volatile const  uint32_t CID0; 
  volatile const  uint32_t CID1; 
  volatile const  uint32_t CID2; 
  volatile const  uint32_t CID3; 
} ITM_Type; 
 
 
  
typedef struct 
{ 
       uint32_t RESERVED0; 
  volatile const  uint32_t ICTR;                           
 
 
 
       uint32_t RESERVED1; 
 
} InterruptType_Type; 
 
 
  
 
typedef struct 
{ 
  volatile const  uint32_t TYPE;                           
  volatile uint32_t CTRL;                           
  volatile uint32_t RNR;                            
  volatile uint32_t RBAR;                           
  volatile uint32_t RASR;                           
  volatile uint32_t RBAR_A1;                        
  volatile uint32_t RASR_A1;                        
  volatile uint32_t RBAR_A2;                        
  volatile uint32_t RASR_A2;                        
  volatile uint32_t RBAR_A3;                        
  volatile uint32_t RASR_A3;                        
} MPU_Type; 
 
 
 
  
typedef struct 
{ 
  volatile uint32_t DHCSR;                          
  volatile  uint32_t DCRSR;                          
  volatile uint32_t DCRDR;                          
  volatile uint32_t DEMCR;                          
} CoreDebug_Type; 
 
 
  
#line 274 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
#line 281 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
#line 311 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
  
 
 
  
 
 
 
 
#line 336 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
  
  
  
  
 
 
 
 
 
 
 
 
 
  
extern uint32_t __get_PSP(void); 
 
 
 
 
 
 
 
 
 
  
extern void __set_PSP(uint32_t topOfProcStack); 
 
 
 
 
 
 
 
 
 
  
extern uint32_t __get_MSP(void); 
 
 
 
 
 
 
 
 
 
  
extern void __set_MSP(uint32_t topOfMainStack); 
 
 
 
 
 
 
 
 
  
extern uint32_t __REV16(uint16_t value); 
 
 
 
 
 
 
 
 
  
extern int32_t __REVSH(int16_t value); 
 
 
#line 502 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t  __get_BASEPRI(void) 
{ 
  register uint32_t __regBasePri         __asm("basepri"); 
  return(__regBasePri); 
} 
 
 
 
 
 
 
 
 
  
static __inline void __set_BASEPRI(uint32_t basePri) 
{ 
  register uint32_t __regBasePri         __asm("basepri"); 
  __regBasePri = (basePri & 0x1ff); 
} 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t __get_PRIMASK(void) 
{ 
  register uint32_t __regPriMask         __asm("primask"); 
  return(__regPriMask); 
} 
 
 
 
 
 
 
 
 
  
static __inline void __set_PRIMASK(uint32_t priMask) 
{ 
  register uint32_t __regPriMask         __asm("primask"); 
  __regPriMask = (priMask); 
} 
 
 
 
 
 
 
 
 
  
static __inline uint32_t __get_FAULTMASK(void) 
{ 
  register uint32_t __regFaultMask       __asm("faultmask"); 
  return(__regFaultMask); 
} 
 
 
 
 
 
 
 
 
  
static __inline void __set_FAULTMASK(uint32_t faultMask) 
{ 
  register uint32_t __regFaultMask       __asm("faultmask"); 
  __regFaultMask = (faultMask & 1); 
} 
 
 
 
 
 
 
 
 
  
static __inline uint32_t __get_CONTROL(void) 
{ 
  register uint32_t __regControl         __asm("control"); 
  return(__regControl); 
} 
 
 
 
 
 
 
 
 
  
static __inline void __set_CONTROL(uint32_t control) 
{ 
  register uint32_t __regControl         __asm("control"); 
  __regControl = control; 
} 
 
 
 
 
 
#line 1044 "C:\\Keil\\\\ARM\\RV31\\INC\\core_cm3.h" 
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 
{ 
  uint32_t reg_value; 
  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                           
   
  reg_value  = ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR;                                                      
  reg_value &= ~((0xFFFFU << 16) | (0x0F << 8));                                
  reg_value  = ((reg_value | (0x5FA << 16) | (PriorityGroupTmp << 8)));    
  ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR = reg_value; 
} 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t NVIC_GetPriorityGrouping(void) 
{ 
  return ((((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR >> 8) & 0x07);                                            
} 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_EnableIRQ(IRQn_Type IRQn) 
{ 
  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));   
} 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_DisableIRQ(IRQn_Type IRQn) 
{ 
  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));   
} 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 
{ 
  return((uint32_t) ((((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));   
} 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_SetPendingIRQ(IRQn_Type IRQn) 
{ 
  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));   
} 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 
{ 
  ((NVIC_Type *) ((0xE000E000) + 0x0100))->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));   
} 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t NVIC_GetActive(IRQn_Type IRQn) 
{ 
  return((uint32_t)((((NVIC_Type *) ((0xE000E000) + 0x0100))->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));   
} 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 
{ 
  if(IRQn < 0) { 
    ((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - 5)) & 0xff); }   
  else { 
    ((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)] = ((priority << (8 - 5)) & 0xff);    }          
} 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t NVIC_GetPriority(IRQn_Type IRQn) 
{ 
 
  if(IRQn < 0) { 
    return((uint32_t)(((SCB_Type *) ((0xE000E000) + 0x0D00))->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - 5)));  }   
  else { 
    return((uint32_t)(((NVIC_Type *) ((0xE000E000) + 0x0100))->IP[(uint32_t)(IRQn)]           >> (8 - 5)));  }   
} 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 
{ 
  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                           
  uint32_t PreemptPriorityBits; 
  uint32_t SubPriorityBits; 
 
  PreemptPriorityBits = ((7 - PriorityGroupTmp) > 5) ? 5 : 7 - PriorityGroupTmp; 
  SubPriorityBits     = ((PriorityGroupTmp + 5) < 7) ? 0 : PriorityGroupTmp - 7 + 5; 
  
  return ( 
           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 
           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1))) 
         ); 
} 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
static __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 
{ 
  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                           
  uint32_t PreemptPriorityBits; 
  uint32_t SubPriorityBits; 
 
  PreemptPriorityBits = ((7 - PriorityGroupTmp) > 5) ? 5 : 7 - PriorityGroupTmp; 
  SubPriorityBits     = ((PriorityGroupTmp + 5) < 7) ? 0 : PriorityGroupTmp - 7 + 5; 
   
  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 
  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1); 
} 
 
 
 
  
 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t SysTick_Config(uint32_t ticks) 
{  
  if (ticks > ((1<<24) -1))  return (1);                                               
 
  ((SysTick_Type *) ((0xE000E000) + 0x0010))->LOAD  =  (ticks & ((1<<24) -1)) - 1;                                        
  NVIC_SetPriority (SysTick_IRQn, (1<<5) - 1);                              
  ((SysTick_Type *) ((0xE000E000) + 0x0010))->VAL   =  (0x00);                                                                
  ((SysTick_Type *) ((0xE000E000) + 0x0010))->CTRL = (1 << 2) | (1<<0) | (1<<1);   
  return (0);                                                                              
} 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
  
static __inline void NVIC_SystemReset(void) 
{ 
  ((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR  = ((0x5FA << 16) | (((SCB_Type *) ((0xE000E000) + 0x0D00))->AIRCR & (0x700)) | (1<<2));   
  __dsb(0);                                                                                             
  while(1);                                                                              
} 
 
 
  
 
 
 
 
 
 
 
 
 
 
 
  
static __inline uint32_t ITM_SendChar (uint32_t ch) 
{ 
  if (ch == '\n') ITM_SendChar('\r'); 
   
  if ((((CoreDebug_Type *) (0xE000EDF0))->DEMCR & (1 << 24))  && 
      (((ITM_Type *) (0xE0000000))->TCR & 1)                  && 
      (((ITM_Type *) (0xE0000000))->TER & (1UL << 0))  )  
  { 
    while (((ITM_Type *) (0xE0000000))->PORT[0].u32 == 0); 
    ((ITM_Type *) (0xE0000000))->PORT[0].u8 = (uint8_t) ch; 
  }   
  return (ch); 
} 
 
 
 
 
 
 
 
  
#line 95 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
#line 1 "C:\\Keil\\ARM\\INC\\NXP\\system_LPC17xx.h" 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 
 
 
 
extern uint32_t SystemFrequency;      
 
 
 
 
 
 
 
 
 
 
  
extern void SystemInit (void); 
 
 
 
 
 
#line 96 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
 
  
  
  
 
#pragma anon_unions 
 
  
typedef struct 
{ 
  volatile uint32_t FLASHCFG;                 
       uint32_t RESERVED0[31]; 
  volatile uint32_t PLL0CON;                  
  volatile uint32_t PLL0CFG; 
  volatile const  uint32_t PLL0STAT; 
  volatile  uint32_t PLL0FEED; 
       uint32_t RESERVED1[4]; 
  volatile uint32_t PLL1CON; 
  volatile uint32_t PLL1CFG; 
  volatile const  uint32_t PLL1STAT; 
  volatile  uint32_t PLL1FEED; 
       uint32_t RESERVED2[4]; 
  volatile uint32_t PCON; 
  volatile uint32_t PCONP; 
       uint32_t RESERVED3[15]; 
  volatile uint32_t CCLKCFG; 
  volatile uint32_t USBCLKCFG; 
  volatile uint32_t CLKSRCSEL; 
       uint32_t RESERVED4[12]; 
  volatile uint32_t EXTINT;                   
       uint32_t RESERVED5; 
  volatile uint32_t EXTMODE; 
  volatile uint32_t EXTPOLAR; 
       uint32_t RESERVED6[12]; 
  volatile uint32_t RSID;                     
       uint32_t RESERVED7[7]; 
  volatile uint32_t SCS;                      
  volatile uint32_t IRCTRIM;                  
  volatile uint32_t PCLKSEL0; 
  volatile uint32_t PCLKSEL1; 
       uint32_t RESERVED8[4]; 
  volatile uint32_t USBIntSt;                 
       uint32_t RESERVED9; 
  volatile uint32_t CLKOUTCFG;                
 } LPC_SC_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t PINSEL0; 
  volatile uint32_t PINSEL1; 
  volatile uint32_t PINSEL2; 
  volatile uint32_t PINSEL3; 
  volatile uint32_t PINSEL4; 
  volatile uint32_t PINSEL5; 
  volatile uint32_t PINSEL6; 
  volatile uint32_t PINSEL7; 
  volatile uint32_t PINSEL8; 
  volatile uint32_t PINSEL9; 
  volatile uint32_t PINSEL10; 
       uint32_t RESERVED0[5]; 
  volatile uint32_t PINMODE0; 
  volatile uint32_t PINMODE1; 
  volatile uint32_t PINMODE2; 
  volatile uint32_t PINMODE3; 
  volatile uint32_t PINMODE4; 
  volatile uint32_t PINMODE5; 
  volatile uint32_t PINMODE6; 
  volatile uint32_t PINMODE7; 
  volatile uint32_t PINMODE8; 
  volatile uint32_t PINMODE9; 
  volatile uint32_t PINMODE_OD0; 
  volatile uint32_t PINMODE_OD1; 
  volatile uint32_t PINMODE_OD2; 
  volatile uint32_t PINMODE_OD3; 
  volatile uint32_t PINMODE_OD4; 
  volatile uint32_t I2CPADCFG; 
} LPC_PINCON_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t FIODIR; 
       uint32_t RESERVED0[3]; 
  volatile uint32_t FIOMASK; 
  volatile uint32_t FIOPIN; 
  volatile uint32_t FIOSET; 
  volatile  uint32_t FIOCLR; 
} LPC_GPIO_TypeDef; 
 
typedef struct 
{ 
  volatile const  uint32_t IntStatus; 
  volatile const  uint32_t IO0IntStatR; 
  volatile const  uint32_t IO0IntStatF; 
  volatile  uint32_t IO0IntClr; 
  volatile uint32_t IO0IntEnR; 
  volatile uint32_t IO0IntEnF; 
       uint32_t RESERVED0[3]; 
  volatile const  uint32_t IO2IntStatR; 
  volatile const  uint32_t IO2IntStatF; 
  volatile  uint32_t IO2IntClr; 
  volatile uint32_t IO2IntEnR; 
  volatile uint32_t IO2IntEnF; 
} LPC_GPIOINT_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t IR; 
  volatile uint32_t TCR; 
  volatile uint32_t TC; 
  volatile uint32_t PR; 
  volatile uint32_t PC; 
  volatile uint32_t MCR; 
  volatile uint32_t MR0; 
  volatile uint32_t MR1; 
  volatile uint32_t MR2; 
  volatile uint32_t MR3; 
  volatile uint32_t CCR; 
  volatile const  uint32_t CR0; 
  volatile const  uint32_t CR1; 
       uint32_t RESERVED0[2]; 
  volatile uint32_t EMR; 
       uint32_t RESERVED1[24]; 
  volatile uint32_t CTCR; 
} LPC_TIM_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t IR; 
  volatile uint32_t TCR; 
  volatile uint32_t TC; 
  volatile uint32_t PR; 
  volatile uint32_t PC; 
  volatile uint32_t MCR; 
  volatile uint32_t MR0; 
  volatile uint32_t MR1; 
  volatile uint32_t MR2; 
  volatile uint32_t MR3; 
  volatile uint32_t CCR; 
  volatile const  uint32_t CR0; 
  volatile const  uint32_t CR1; 
  volatile const  uint32_t CR2; 
  volatile const  uint32_t CR3; 
       uint32_t RESERVED0; 
  volatile uint32_t MR4; 
  volatile uint32_t MR5; 
  volatile uint32_t MR6; 
  volatile uint32_t PCR; 
  volatile uint32_t LER; 
       uint32_t RESERVED1[7]; 
  volatile uint32_t CTCR; 
} LPC_PWM_TypeDef; 
 
  
typedef struct 
{ 
  union { 
  volatile const  uint8_t  RBR; 
  volatile  uint8_t  THR; 
  volatile uint8_t  DLL; 
       uint32_t RESERVED0; 
  }; 
  union { 
  volatile uint8_t  DLM; 
  volatile uint32_t IER; 
  }; 
  union { 
  volatile const  uint32_t IIR; 
  volatile  uint8_t  FCR; 
  }; 
  volatile uint8_t  LCR; 
       uint8_t  RESERVED1[7]; 
  volatile const  uint8_t  LSR; 
       uint8_t  RESERVED2[7]; 
  volatile uint8_t  SCR; 
       uint8_t  RESERVED3[3]; 
  volatile uint32_t ACR; 
  volatile uint8_t  ICR; 
       uint8_t  RESERVED4[3]; 
  volatile uint8_t  FDR; 
       uint8_t  RESERVED5[7]; 
  volatile uint8_t  TER; 
       uint8_t  RESERVED6[39]; 
  volatile const  uint8_t  FIFOLVL; 
} LPC_UART_TypeDef; 
 
typedef struct 
{ 
  union { 
  volatile const  uint8_t  RBR; 
  volatile  uint8_t  THR; 
  volatile uint8_t  DLL; 
       uint32_t RESERVED0; 
  }; 
  union { 
  volatile uint8_t  DLM; 
  volatile uint32_t IER; 
  }; 
  union { 
  volatile const  uint32_t IIR; 
  volatile  uint8_t  FCR; 
  }; 
  volatile uint8_t  LCR; 
       uint8_t  RESERVED1[7]; 
  volatile const  uint8_t  LSR; 
       uint8_t  RESERVED2[7]; 
  volatile uint8_t  SCR; 
       uint8_t  RESERVED3[3]; 
  volatile uint32_t ACR; 
  volatile uint8_t  ICR; 
       uint8_t  RESERVED4[3]; 
  volatile uint8_t  FDR; 
       uint8_t  RESERVED5[7]; 
  volatile uint8_t  TER; 
       uint8_t  RESERVED6[39]; 
  volatile const  uint8_t  FIFOLVL; 
       uint8_t  RESERVED7[363]; 
  volatile uint32_t DMAREQSEL; 
} LPC_UART0_TypeDef; 
 
typedef struct 
{ 
  union { 
  volatile const  uint8_t  RBR; 
  volatile  uint8_t  THR; 
  volatile uint8_t  DLL; 
       uint32_t RESERVED0; 
  }; 
  union { 
  volatile uint8_t  DLM; 
  volatile uint32_t IER; 
  }; 
  union { 
  volatile const  uint32_t IIR; 
  volatile  uint8_t  FCR; 
  }; 
  volatile uint8_t  LCR; 
       uint8_t  RESERVED1[3]; 
  volatile uint8_t  MCR; 
       uint8_t  RESERVED2[3]; 
  volatile const  uint8_t  LSR; 
       uint8_t  RESERVED3[3]; 
  volatile const  uint8_t  MSR; 
       uint8_t  RESERVED4[3]; 
  volatile uint8_t  SCR; 
       uint8_t  RESERVED5[3]; 
  volatile uint32_t ACR; 
       uint32_t RESERVED6; 
  volatile uint32_t FDR; 
       uint32_t RESERVED7; 
  volatile uint8_t  TER; 
       uint8_t  RESERVED8[27]; 
  volatile uint8_t  RS485CTRL; 
       uint8_t  RESERVED9[3]; 
  volatile uint8_t  ADRMATCH; 
       uint8_t  RESERVED10[3]; 
  volatile uint8_t  RS485DLY; 
       uint8_t  RESERVED11[3]; 
  volatile const  uint8_t  FIFOLVL; 
} LPC_UART1_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t SPCR; 
  volatile  uint32_t SPSR; 
  volatile uint32_t SPDR; 
  volatile uint32_t SPCCR; 
       uint32_t RESERVED0[3]; 
  volatile uint32_t SPINT; 
} LPC_SPI_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t CR0; 
  volatile uint32_t CR1; 
  volatile uint32_t DR; 
  volatile const  uint32_t SR; 
  volatile uint32_t CPSR; 
  volatile uint32_t IMSC; 
  volatile uint32_t RIS; 
  volatile uint32_t MIS; 
  volatile uint32_t ICR; 
  volatile uint32_t DMACR; 
} LPC_SSP_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t I2CONSET; 
  volatile const  uint32_t I2STAT; 
  volatile uint32_t I2DAT; 
  volatile uint32_t I2ADR0; 
  volatile uint32_t I2SCLH; 
  volatile uint32_t I2SCLL; 
  volatile  uint32_t I2CONCLR; 
  volatile uint32_t MMCTRL; 
  volatile uint32_t I2ADR1; 
  volatile uint32_t I2ADR2; 
  volatile uint32_t I2ADR3; 
  volatile const  uint32_t I2DATA_BUFFER; 
  volatile uint32_t I2MASK0; 
  volatile uint32_t I2MASK1; 
  volatile uint32_t I2MASK2; 
  volatile uint32_t I2MASK3; 
} LPC_I2C_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t I2SDAO; 
  volatile uint32_t I2SDAI; 
  volatile  uint32_t I2STXFIFO; 
  volatile const  uint32_t I2SRXFIFO; 
  volatile const  uint32_t I2SSTATE; 
  volatile uint32_t I2SDMA1; 
  volatile uint32_t I2SDMA2; 
  volatile uint32_t I2SIRQ; 
  volatile uint32_t I2STXRATE; 
  volatile uint32_t I2SRXRATE; 
  volatile uint32_t I2STXBITRATE; 
  volatile uint32_t I2SRXBITRATE; 
  volatile uint32_t I2STXMODE; 
  volatile uint32_t I2SRXMODE; 
} LPC_I2S_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t RICOMPVAL; 
  volatile uint32_t RIMASK; 
  volatile uint8_t  RICTRL; 
       uint8_t  RESERVED0[3]; 
  volatile uint32_t RICOUNTER; 
} LPC_RIT_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint8_t  ILR; 
       uint8_t  RESERVED0[7]; 
  volatile uint8_t  CCR; 
       uint8_t  RESERVED1[3]; 
  volatile uint8_t  CIIR; 
       uint8_t  RESERVED2[3]; 
  volatile uint8_t  AMR; 
       uint8_t  RESERVED3[3]; 
  volatile const  uint32_t CTIME0; 
  volatile const  uint32_t CTIME1; 
  volatile const  uint32_t CTIME2; 
  volatile uint8_t  SEC; 
       uint8_t  RESERVED4[3]; 
  volatile uint8_t  MIN; 
       uint8_t  RESERVED5[3]; 
  volatile uint8_t  HOUR; 
       uint8_t  RESERVED6[3]; 
  volatile uint8_t  DOM; 
       uint8_t  RESERVED7[3]; 
  volatile uint8_t  DOW; 
       uint8_t  RESERVED8[3]; 
  volatile uint16_t DOY; 
       uint16_t RESERVED9; 
  volatile uint8_t  MONTH; 
       uint8_t  RESERVED10[3]; 
  volatile uint16_t YEAR; 
       uint16_t RESERVED11; 
  volatile uint32_t CALIBRATION; 
  volatile uint32_t GPREG0; 
  volatile uint32_t GPREG1; 
  volatile uint32_t GPREG2; 
  volatile uint32_t GPREG3; 
  volatile uint32_t GPREG4; 
  volatile uint8_t  RTC_AUXEN; 
       uint8_t  RESERVED12[3]; 
  volatile uint8_t  RTC_AUX; 
       uint8_t  RESERVED13[3]; 
  volatile uint8_t  ALSEC; 
       uint8_t  RESERVED14[3]; 
  volatile uint8_t  ALMIN; 
       uint8_t  RESERVED15[3]; 
  volatile uint8_t  ALHOUR; 
       uint8_t  RESERVED16[3]; 
  volatile uint8_t  ALDOM; 
       uint8_t  RESERVED17[3]; 
  volatile uint8_t  ALDOW; 
       uint8_t  RESERVED18[3]; 
  volatile uint16_t ALDOY; 
       uint16_t RESERVED19; 
  volatile uint8_t  ALMON; 
       uint8_t  RESERVED20[3]; 
  volatile uint16_t ALYEAR; 
       uint16_t RESERVED21; 
} LPC_RTC_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint8_t  WDMOD; 
       uint8_t  RESERVED0[3]; 
  volatile uint32_t WDTC; 
  volatile  uint8_t  WDFEED; 
       uint8_t  RESERVED1[3]; 
  volatile const  uint32_t WDTV; 
  volatile uint32_t WDCLKSEL; 
} LPC_WDT_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t ADCR; 
  volatile uint32_t ADGDR; 
       uint32_t RESERVED0; 
  volatile uint32_t ADINTEN; 
  volatile const  uint32_t ADDR0; 
  volatile const  uint32_t ADDR1; 
  volatile const  uint32_t ADDR2; 
  volatile const  uint32_t ADDR3; 
  volatile const  uint32_t ADDR4; 
  volatile const  uint32_t ADDR5; 
  volatile const  uint32_t ADDR6; 
  volatile const  uint32_t ADDR7; 
  volatile const  uint32_t ADSTAT; 
  volatile uint32_t ADTRM; 
} LPC_ADC_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t DACR; 
  volatile uint32_t DACCTRL; 
  volatile uint16_t DACCNTVAL; 
} LPC_DAC_TypeDef; 
 
  
typedef struct 
{ 
  volatile const  uint32_t MCCON; 
  volatile  uint32_t MCCON_SET; 
  volatile  uint32_t MCCON_CLR; 
  volatile const  uint32_t MCCAPCON; 
  volatile  uint32_t MCCAPCON_SET; 
  volatile  uint32_t MCCAPCON_CLR; 
  volatile uint32_t MCTIM0; 
  volatile uint32_t MCTIM1; 
  volatile uint32_t MCTIM2; 
  volatile uint32_t MCPER0; 
  volatile uint32_t MCPER1; 
  volatile uint32_t MCPER2; 
  volatile uint32_t MCPW0; 
  volatile uint32_t MCPW1; 
  volatile uint32_t MCPW2; 
  volatile uint32_t MCDEADTIME; 
  volatile uint32_t MCCCP; 
  volatile uint32_t MCCR0; 
  volatile uint32_t MCCR1; 
  volatile uint32_t MCCR2; 
  volatile const  uint32_t MCINTEN; 
  volatile  uint32_t MCINTEN_SET; 
  volatile  uint32_t MCINTEN_CLR; 
  volatile const  uint32_t MCCNTCON; 
  volatile  uint32_t MCCNTCON_SET; 
  volatile  uint32_t MCCNTCON_CLR; 
  volatile const  uint32_t MCINTFLAG; 
  volatile  uint32_t MCINTFLAG_SET; 
  volatile  uint32_t MCINTFLAG_CLR; 
  volatile  uint32_t MCCAP_CLR; 
} LPC_MCPWM_TypeDef; 
 
  
typedef struct 
{ 
  volatile  uint32_t QEICON; 
  volatile const  uint32_t QEISTAT; 
  volatile uint32_t QEICONF; 
  volatile const  uint32_t QEIPOS; 
  volatile uint32_t QEIMAXPOS; 
  volatile uint32_t CMPOS0; 
  volatile uint32_t CMPOS1; 
  volatile uint32_t CMPOS2; 
  volatile const  uint32_t INXCNT; 
  volatile uint32_t INXCMP; 
  volatile uint32_t QEILOAD; 
  volatile const  uint32_t QEITIME; 
  volatile const  uint32_t QEIVEL; 
  volatile const  uint32_t QEICAP; 
  volatile uint32_t VELCOMP; 
  volatile uint32_t FILTER; 
       uint32_t RESERVED0[998]; 
  volatile  uint32_t QEIIEC; 
  volatile  uint32_t QEIIES; 
  volatile const  uint32_t QEIINTSTAT; 
  volatile const  uint32_t QEIIE; 
  volatile  uint32_t QEICLR; 
  volatile  uint32_t QEISET; 
} LPC_QEI_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t mask[512];                
} LPC_CANAF_RAM_TypeDef; 
 
typedef struct                            
{ 
  volatile uint32_t AFMR; 
  volatile uint32_t SFF_sa; 
  volatile uint32_t SFF_GRP_sa; 
  volatile uint32_t EFF_sa; 
  volatile uint32_t EFF_GRP_sa; 
  volatile uint32_t ENDofTable; 
  volatile const  uint32_t LUTerrAd; 
  volatile const  uint32_t LUTerr; 
  volatile uint32_t FCANIE; 
  volatile uint32_t FCANIC0; 
  volatile uint32_t FCANIC1; 
} LPC_CANAF_TypeDef; 
 
typedef struct                            
{ 
  volatile const  uint32_t CANTxSR; 
  volatile const  uint32_t CANRxSR; 
  volatile const  uint32_t CANMSR; 
} LPC_CANCR_TypeDef; 
 
typedef struct                            
{ 
  volatile uint32_t MOD; 
  volatile  uint32_t CMR; 
  volatile uint32_t GSR; 
  volatile const  uint32_t ICR; 
  volatile uint32_t IER; 
  volatile uint32_t BTR; 
  volatile uint32_t EWL; 
  volatile const  uint32_t SR; 
  volatile uint32_t RFS; 
  volatile uint32_t RID; 
  volatile uint32_t RDA; 
  volatile uint32_t RDB; 
  volatile uint32_t TFI1; 
  volatile uint32_t TID1; 
  volatile uint32_t TDA1; 
  volatile uint32_t TDB1; 
  volatile uint32_t TFI2; 
  volatile uint32_t TID2; 
  volatile uint32_t TDA2; 
  volatile uint32_t TDB2; 
  volatile uint32_t TFI3; 
  volatile uint32_t TID3; 
  volatile uint32_t TDA3; 
  volatile uint32_t TDB3; 
} LPC_CAN_TypeDef; 
 
  
typedef struct                            
{ 
  volatile const  uint32_t DMACIntStat; 
  volatile const  uint32_t DMACIntTCStat; 
  volatile  uint32_t DMACIntTCClear; 
  volatile const  uint32_t DMACIntErrStat; 
  volatile  uint32_t DMACIntErrClr; 
  volatile const  uint32_t DMACRawIntTCStat; 
  volatile const  uint32_t DMACRawIntErrStat; 
  volatile const  uint32_t DMACEnbldChns; 
  volatile uint32_t DMACSoftBReq; 
  volatile uint32_t DMACSoftSReq; 
  volatile uint32_t DMACSoftLBReq; 
  volatile uint32_t DMACSoftLSReq; 
  volatile uint32_t DMACConfig; 
  volatile uint32_t DMACSync; 
} LPC_GPDMA_TypeDef; 
 
typedef struct                            
{ 
  volatile uint32_t DMACCSrcAddr; 
  volatile uint32_t DMACCDestAddr; 
  volatile uint32_t DMACCLLI; 
  volatile uint32_t DMACCControl; 
  volatile uint32_t DMACCConfig; 
} LPC_GPDMACH_TypeDef; 
 
  
typedef struct 
{ 
  volatile const  uint32_t HcRevision;               
  volatile uint32_t HcControl; 
  volatile uint32_t HcCommandStatus; 
  volatile uint32_t HcInterruptStatus; 
  volatile uint32_t HcInterruptEnable; 
  volatile uint32_t HcInterruptDisable; 
  volatile uint32_t HcHCCA; 
  volatile const  uint32_t HcPeriodCurrentED; 
  volatile uint32_t HcControlHeadED; 
  volatile uint32_t HcControlCurrentED; 
  volatile uint32_t HcBulkHeadED; 
  volatile uint32_t HcBulkCurrentED; 
  volatile const  uint32_t HcDoneHead; 
  volatile uint32_t HcFmInterval; 
  volatile const  uint32_t HcFmRemaining; 
  volatile const  uint32_t HcFmNumber; 
  volatile uint32_t HcPeriodicStart; 
  volatile uint32_t HcLSTreshold; 
  volatile uint32_t HcRhDescriptorA; 
  volatile uint32_t HcRhDescriptorB; 
  volatile uint32_t HcRhStatus; 
  volatile uint32_t HcRhPortStatus1; 
  volatile uint32_t HcRhPortStatus2; 
       uint32_t RESERVED0[40]; 
  volatile const  uint32_t Module_ID; 
 
  volatile const  uint32_t OTGIntSt;                 
  volatile uint32_t OTGIntEn; 
  volatile  uint32_t OTGIntSet; 
  volatile  uint32_t OTGIntClr; 
  volatile uint32_t OTGStCtrl; 
  volatile uint32_t OTGTmr; 
       uint32_t RESERVED1[58]; 
 
  volatile const  uint32_t USBDevIntSt;              
  volatile uint32_t USBDevIntEn; 
  volatile  uint32_t USBDevIntClr; 
  volatile  uint32_t USBDevIntSet; 
 
  volatile  uint32_t USBCmdCode;               
  volatile const  uint32_t USBCmdData; 
 
  volatile const  uint32_t USBRxData;                
  volatile  uint32_t USBTxData; 
  volatile const  uint32_t USBRxPLen; 
  volatile  uint32_t USBTxPLen; 
  volatile uint32_t USBCtrl; 
  volatile  uint32_t USBDevIntPri; 
 
  volatile const  uint32_t USBEpIntSt;               
  volatile uint32_t USBEpIntEn; 
  volatile  uint32_t USBEpIntClr; 
  volatile  uint32_t USBEpIntSet; 
  volatile  uint32_t USBEpIntPri; 
 
  volatile uint32_t USBReEp;                  
  volatile  uint32_t USBEpInd; 
  volatile uint32_t USBMaxPSize; 
 
  volatile const  uint32_t USBDMARSt;                
  volatile  uint32_t USBDMARClr; 
  volatile  uint32_t USBDMARSet; 
       uint32_t RESERVED2[9]; 
  volatile uint32_t USBUDCAH; 
  volatile const  uint32_t USBEpDMASt; 
  volatile  uint32_t USBEpDMAEn; 
  volatile  uint32_t USBEpDMADis; 
  volatile const  uint32_t USBDMAIntSt; 
  volatile uint32_t USBDMAIntEn; 
       uint32_t RESERVED3[2]; 
  volatile const  uint32_t USBEoTIntSt; 
  volatile  uint32_t USBEoTIntClr; 
  volatile  uint32_t USBEoTIntSet; 
  volatile const  uint32_t USBNDDRIntSt; 
  volatile  uint32_t USBNDDRIntClr; 
  volatile  uint32_t USBNDDRIntSet; 
  volatile const  uint32_t USBSysErrIntSt; 
  volatile  uint32_t USBSysErrIntClr; 
  volatile  uint32_t USBSysErrIntSet; 
       uint32_t RESERVED4[15]; 
 
  volatile const  uint32_t I2C_RX;                   
  volatile  uint32_t I2C_WO; 
  volatile const  uint32_t I2C_STS; 
  volatile uint32_t I2C_CTL; 
  volatile uint32_t I2C_CLKHI; 
  volatile  uint32_t I2C_CLKLO; 
       uint32_t RESERVED5[823]; 
 
  union { 
  volatile uint32_t USBClkCtrl;               
  volatile uint32_t OTGClkCtrl; 
  }; 
  union { 
  volatile const  uint32_t USBClkSt; 
  volatile const  uint32_t OTGClkSt; 
  }; 
} LPC_USB_TypeDef; 
 
  
typedef struct 
{ 
  volatile uint32_t MAC1;                     
  volatile uint32_t MAC2; 
  volatile uint32_t IPGT; 
  volatile uint32_t IPGR; 
  volatile uint32_t CLRT; 
  volatile uint32_t MAXF; 
  volatile uint32_t SUPP; 
  volatile uint32_t TEST; 
  volatile uint32_t MCFG; 
  volatile uint32_t MCMD; 
  volatile uint32_t MADR; 
  volatile  uint32_t MWTD; 
  volatile const  uint32_t MRDD; 
  volatile const  uint32_t MIND; 
       uint32_t RESERVED0[2]; 
  volatile uint32_t SA0; 
  volatile uint32_t SA1; 
  volatile uint32_t SA2; 
       uint32_t RESERVED1[45]; 
  volatile uint32_t Command;                  
  volatile const  uint32_t Status; 
  volatile uint32_t RxDescriptor; 
  volatile uint32_t RxStatus; 
  volatile uint32_t RxDescriptorNumber; 
  volatile const  uint32_t RxProduceIndex; 
  volatile uint32_t RxConsumeIndex; 
  volatile uint32_t TxDescriptor; 
  volatile uint32_t TxStatus; 
  volatile uint32_t TxDescriptorNumber; 
  volatile uint32_t TxProduceIndex; 
  volatile const  uint32_t TxConsumeIndex; 
       uint32_t RESERVED2[10]; 
  volatile const  uint32_t TSV0; 
  volatile const  uint32_t TSV1; 
  volatile const  uint32_t RSV; 
       uint32_t RESERVED3[3]; 
  volatile uint32_t FlowControlCounter; 
  volatile const  uint32_t FlowControlStatus; 
       uint32_t RESERVED4[34]; 
  volatile uint32_t RxFilterCtrl;             
  volatile uint32_t RxFilterWoLStatus; 
  volatile uint32_t RxFilterWoLClear; 
       uint32_t RESERVED5; 
  volatile uint32_t HashFilterL; 
  volatile uint32_t HashFilterH; 
       uint32_t RESERVED6[882]; 
  volatile const  uint32_t IntStatus;                
  volatile uint32_t IntEnable; 
  volatile  uint32_t IntClear; 
  volatile  uint32_t IntSet; 
       uint32_t RESERVED7; 
  volatile uint32_t PowerDown; 
       uint32_t RESERVED8; 
  volatile uint32_t Module_ID; 
} LPC_EMAC_TypeDef; 
 
#pragma no_anon_unions 
 
 
  
  
  
  
#line 856 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
  
#line 877 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
  
#line 891 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
  
#line 904 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
  
 
 
 
 
 
 
 
  
  
  
#line 963 "C:\\Keil\\ARM\\INC\\NXP\\LPC17xx.H" 
 
#line 21 "Serial.c" 
#line 1 "Serial.h" 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  
 
 
 
 
extern void SER_init      (int uart); 
extern int  SER_getChar   (int uart); 
extern int  SER_getChar_nb(int uart); 
extern int  SER_putChar   (int uart, int c); 
extern void SER_putString (int uart, unsigned char *s); 
 
#line 22 "Serial.c" 
 
 
 
  
void SER_init (int uart) { 
 
    
  if (uart == 0) {                                 
    ((LPC_PINCON_TypeDef *) ((0x40000000UL) + 0x2C000) )->PINSEL0 |= (1 << 4);               
    ((LPC_PINCON_TypeDef *) ((0x40000000UL) + 0x2C000) )->PINSEL0 |= (1 << 6);               
 
    
  } else {                                         
    ((LPC_PINCON_TypeDef *) ((0x40000000UL) + 0x2C000) )->PINSEL4 |= (2 << 0);               
    ((LPC_PINCON_TypeDef *) ((0x40000000UL) + 0x2C000) )->PINSEL4 |= (2 << 2);               
 
    
  } 
 
  ((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->LCR    = 0x83;                            
  ((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->DLL    = 6;                               
  ((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->FDR    = 0x85;                            
  ((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->DLM    = 0;                               
  ((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->LCR    = 0x03;                            
} 
 
 
 
 
  
int SER_putChar (int uart, int c) { 
   
 
   
  while (!(((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->LSR & 0x20)); 
  return (((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->THR = c); 
} 
 
 
 
 
  
int SER_getChar (int uart) { 
  
 
   
  while (!(((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->LSR & 0x01)); 
  return (((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->RBR); 
} 
 
 
 
 
  
int SER_getChar_nb (int uart) { 
   
 
  
  if (((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->LSR & 0x01) 
    return (((LPC_UART0_TypeDef *) ((0x40000000UL) + 0x0C000) )->RBR); 
  else 
    return 0; 
} 
 
 
 
 
  
void SER_putString (int uart, unsigned char *s) { 
 
  while (*s != 0) { 
   SER_putChar(uart, *s++); 
  } 
}