www.pudn.com > aes_core.rar > design_spec.dc

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#
# Design Specification
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# Author: Rudolf Usselmann
#         rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
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# ==============================================
# Setup Design Parameters

set design_files {aes_rcon aes_sbox aes_key_expand_128 aes_cipher_top}
set design_name  aes_cipher_top
set active_design aes_cipher_top
 
#set design_files {aes_rcon aes_inv_sbox aes_key_expand_128 aes_inv_cipher_top}
#set design_name  aes_inv_cipher_top
#set active_design aes_inv_cipher_top
 
# Next Statement defines all clocks and resets in the design
set special_net {clk}
 
set hdl_src_dir ../../rtl/verilog/