www.pudn.com > NCO.rar > shift_taps_k4n.tdf, change:2010-05-05,size:2784b


--altshift_taps CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" NUMBER_OF_TAPS=1 TAP_DISTANCE=28 WIDTH=2 aclr clken clock shiftin taps CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO" 
--VERSION_BEGIN 9.0 cbx_altdpram 2008:05:19:10:27:12:SJ cbx_altshift_taps 2008:05:19:11:04:47:SJ cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION altsyncram_t0b1 (aclr0, address_a[4..0], address_b[4..0], clock0, clocken0, data_a[1..0], wren_a) 
RETURNS ( q_b[1..0]); 
FUNCTION cntr_lpf (clk_en, clock) 
RETURNS ( q[4..0]); 
FUNCTION cntr_b9h (aset, clk_en, clock, cnt_en) 
RETURNS ( cout, q[4..0]); 
 
--synthesis_resources = lut 10 M9K 1 reg 11  
SUBDESIGN shift_taps_k4n 
(  
	aclr	:	input; 
	clken	:	input; 
	clock	:	input; 
	shiftin[1..0]	:	input; 
	shiftout[1..0]	:	output; 
	taps[1..0]	:	output; 
)  
VARIABLE  
	altsyncram2 : altsyncram_t0b1; 
	dffe4 : dffe; 
	cntr1 : cntr_lpf; 
	cntr3 : cntr_b9h; 
 
BEGIN  
	altsyncram2.aclr0 = dffe4.q; 
	altsyncram2.address_a[] = cntr1.q[]; 
	altsyncram2.address_b[] = cntr1.q[]; 
	altsyncram2.clock0 = clock; 
	altsyncram2.clocken0 = clken; 
	altsyncram2.data_a[] = ( shiftin[]); 
	altsyncram2.wren_a = B"1"; 
	dffe4.clk = clock; 
	dffe4.d = (! cntr3.cout); 
	dffe4.ena = clken; 
	dffe4.prn = (! aclr); 
	cntr1.clk_en = clken; 
	cntr1.clock = clock; 
	cntr3.aset = aclr; 
	cntr3.clk_en = clken; 
	cntr3.clock = clock; 
	cntr3.cnt_en = (! cntr3.cout); 
	shiftout[1..0] = altsyncram2.q_b[1..0]; 
	taps[] = altsyncram2.q_b[]; 
END; 
--VALID FILE