www.pudn.com > NCO.rar > cntr_tnf.tdf, change:2010-05-05,size:3249b


--lpm_counter CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone III" lpm_direction="UP" lpm_modulus=3 lpm_port_updown="PORT_UNUSED" lpm_width=2 clk_en clock q 
--VERSION_BEGIN 9.0 cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION cmpr_ffc (dataa[1..0], datab[1..0]) 
RETURNS ( aeb); 
 
--synthesis_resources = lut 2 reg 2  
SUBDESIGN cntr_tnf 
(  
	clk_en	:	input; 
	clock	:	input; 
	q[1..0]	:	output; 
)  
VARIABLE  
	counter_reg_bit[1..0] : dffe; 
	add_sub8_result_int[2..0]	:	WIRE; 
	add_sub8_cout	:	WIRE; 
	add_sub8_dataa[1..0]	:	WIRE; 
	add_sub8_datab[1..0]	:	WIRE; 
	add_sub8_result[1..0]	:	WIRE; 
	cmpr9 : cmpr_ffc; 
	aclr_actual	: WIRE; 
	add_sub_one_w[1..0]	: WIRE; 
	add_value_w[1..0]	: WIRE; 
	cnt_en	: NODE; 
	compare_result	: WIRE; 
	cout_actual	: WIRE; 
	current_reg_q_w[1..0]	: WIRE; 
	custom_cout_w	: WIRE; 
	modulus_bus[1..0]	: WIRE; 
	modulus_trigger	: WIRE; 
	modulus_trigger_value_w[1..0]	: WIRE; 
	safe_q[1..0]	: WIRE; 
	time_to_clear	: WIRE; 
	trigger_mux_w[1..0]	: WIRE; 
	updown_dir	: WIRE; 
 
BEGIN  
	counter_reg_bit[].clk = clock; 
	counter_reg_bit[].clrn = (! aclr_actual); 
	counter_reg_bit[].d = trigger_mux_w[]; 
	counter_reg_bit[].ena = (clk_en & cnt_en); 
	add_sub8_result_int[] = (0, add_sub8_dataa[]) + (0, add_sub8_datab[]); 
	add_sub8_result[] = add_sub8_result_int[1..0]; 
	add_sub8_cout = add_sub8_result_int[2]; 
	add_sub8_dataa[] = current_reg_q_w[]; 
	add_sub8_datab[] = add_value_w[]; 
	cmpr9.dataa[] = safe_q[]; 
	cmpr9.datab[] = modulus_bus[]; 
	aclr_actual = B"0"; 
	add_sub_one_w[] = add_sub8_result[]; 
	add_value_w[] = B"01"; 
	cnt_en = VCC; 
	compare_result = cmpr9.aeb; 
	cout_actual = (custom_cout_w # (time_to_clear & updown_dir)); 
	current_reg_q_w[] = counter_reg_bit[].q; 
	custom_cout_w = (add_sub8_cout & add_value_w[0..0]); 
	modulus_bus[] = B"10"; 
	modulus_trigger = cout_actual; 
	modulus_trigger_value_w[] = ((! updown_dir) & modulus_bus[]); 
	q[] = safe_q[]; 
	safe_q[] = counter_reg_bit[].q; 
	time_to_clear = compare_result; 
	trigger_mux_w[] = (((! modulus_trigger) & add_sub_one_w[]) # (modulus_trigger & modulus_trigger_value_w[])); 
	updown_dir = B"1"; 
END; 
--VALID FILE