www.pudn.com > NCO.rar > altsyncram_o761.tdf, change:2010-05-05,size:30149b


--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone III" LOW_POWER_MODE="AUTO" NUMWORDS_A=3 NUMWORDS_B=3 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="CLEAR0" OUTDATA_REG_B="CLOCK1" WIDTH_A=25 WIDTH_B=25 WIDTHAD_A=2 WIDTHAD_B=2 aclr0 address_a address_b clock0 clock1 clocken0 clocken1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 
--VERSION_BEGIN 9.0 cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ  VERSION_END 
 
 
-- Copyright (C) 1991-2009 Altera Corporation 
--  Your use of Altera Corporation's design tools, logic functions  
--  and other software and tools, and its AMPP partner logic  
--  functions, and any output files from any of the foregoing  
--  (including device programming or simulation files), and any  
--  associated documentation or information are expressly subject  
--  to the terms and conditions of the Altera Program License  
--  Subscription Agreement, Altera MegaCore Function License  
--  Agreement, or other applicable license agreement, including,  
--  without limitation, that your use is for the sole purpose of  
--  programming logic devices manufactured by Altera and sold by  
--  Altera or its authorized distributors.  Please refer to the  
--  applicable agreement for further details. 
 
 
FUNCTION cycloneiii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) 
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE) 
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); 
 
--synthesis_resources = M9K 1  
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; 
 
SUBDESIGN altsyncram_o761 
(  
	aclr0	:	input; 
	address_a[1..0]	:	input; 
	address_b[1..0]	:	input; 
	clock0	:	input; 
	clock1	:	input; 
	clocken0	:	input; 
	clocken1	:	input; 
	data_a[24..0]	:	input; 
	q_b[24..0]	:	output; 
	wren_a	:	input; 
)  
VARIABLE  
	ram_block7a0 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 0, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 0, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a1 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 1, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 1, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a2 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 2, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 2, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a3 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 3, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 3, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a4 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 4, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 4, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a5 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 5, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 5, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a6 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 6, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 6, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a7 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 7, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 7, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a8 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 8, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 8, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a9 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 9, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 9, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a10 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 10, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 10, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a11 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 11, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 11, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a12 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 12, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 12, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a13 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 13, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 13, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a14 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 14, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 14, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a15 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 15, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 15, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a16 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 16, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 16, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a17 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 17, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 17, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a18 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 18, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 18, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a19 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 19, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 19, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a20 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 20, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 20, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a21 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 21, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 21, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a22 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 22, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 22, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a23 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 23, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 23, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	ram_block7a24 : cycloneiii_ram_block 
		WITH ( 
			CLK0_CORE_CLOCK_ENABLE = "ena0", 
			CLK0_INPUT_CLOCK_ENABLE = "ena0", 
			CLK1_OUTPUT_CLOCK_ENABLE = "ena1", 
			CONNECTIVITY_CHECKING = "OFF", 
			LOGICAL_RAM_NAME = "ALTSYNCRAM", 
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care", 
			OPERATION_MODE = "dual_port", 
			PORT_A_ADDRESS_WIDTH = 2, 
			PORT_A_DATA_WIDTH = 1, 
			PORT_A_FIRST_ADDRESS = 0, 
			PORT_A_FIRST_BIT_NUMBER = 24, 
			PORT_A_LAST_ADDRESS = 2, 
			PORT_A_LOGICAL_RAM_DEPTH = 3, 
			PORT_A_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_ADDRESS_CLEAR = "none", 
			PORT_B_ADDRESS_CLOCK = "clock0", 
			PORT_B_ADDRESS_WIDTH = 2, 
			PORT_B_DATA_OUT_CLEAR = "clear0", 
			PORT_B_DATA_OUT_CLOCK = "clock1", 
			PORT_B_DATA_WIDTH = 1, 
			PORT_B_FIRST_ADDRESS = 0, 
			PORT_B_FIRST_BIT_NUMBER = 24, 
			PORT_B_LAST_ADDRESS = 2, 
			PORT_B_LOGICAL_RAM_DEPTH = 3, 
			PORT_B_LOGICAL_RAM_WIDTH = 25, 
			PORT_B_READ_ENABLE_CLOCK = "clock0", 
			RAM_BLOCK_TYPE = "AUTO" 
		); 
	address_a_wire[1..0]	: WIRE; 
	address_b_wire[1..0]	: WIRE; 
 
BEGIN  
	ram_block7a[24..0].clk0 = clock0; 
	ram_block7a[24..0].clk1 = clock1; 
	ram_block7a[24..0].clr0 = aclr0; 
	ram_block7a[24..0].ena0 = clocken0; 
	ram_block7a[24..0].ena1 = clocken1; 
	ram_block7a[24..0].portaaddr[] = ( address_a_wire[1..0]); 
	ram_block7a[0].portadatain[] = ( data_a[0..0]); 
	ram_block7a[1].portadatain[] = ( data_a[1..1]); 
	ram_block7a[2].portadatain[] = ( data_a[2..2]); 
	ram_block7a[3].portadatain[] = ( data_a[3..3]); 
	ram_block7a[4].portadatain[] = ( data_a[4..4]); 
	ram_block7a[5].portadatain[] = ( data_a[5..5]); 
	ram_block7a[6].portadatain[] = ( data_a[6..6]); 
	ram_block7a[7].portadatain[] = ( data_a[7..7]); 
	ram_block7a[8].portadatain[] = ( data_a[8..8]); 
	ram_block7a[9].portadatain[] = ( data_a[9..9]); 
	ram_block7a[10].portadatain[] = ( data_a[10..10]); 
	ram_block7a[11].portadatain[] = ( data_a[11..11]); 
	ram_block7a[12].portadatain[] = ( data_a[12..12]); 
	ram_block7a[13].portadatain[] = ( data_a[13..13]); 
	ram_block7a[14].portadatain[] = ( data_a[14..14]); 
	ram_block7a[15].portadatain[] = ( data_a[15..15]); 
	ram_block7a[16].portadatain[] = ( data_a[16..16]); 
	ram_block7a[17].portadatain[] = ( data_a[17..17]); 
	ram_block7a[18].portadatain[] = ( data_a[18..18]); 
	ram_block7a[19].portadatain[] = ( data_a[19..19]); 
	ram_block7a[20].portadatain[] = ( data_a[20..20]); 
	ram_block7a[21].portadatain[] = ( data_a[21..21]); 
	ram_block7a[22].portadatain[] = ( data_a[22..22]); 
	ram_block7a[23].portadatain[] = ( data_a[23..23]); 
	ram_block7a[24].portadatain[] = ( data_a[24..24]); 
	ram_block7a[24..0].portawe = wren_a; 
	ram_block7a[24..0].portbaddr[] = ( address_b_wire[1..0]); 
	ram_block7a[24..0].portbre = B"1111111111111111111111111"; 
	address_a_wire[] = address_a[]; 
	address_b_wire[] = address_b[]; 
	q_b[] = ( ram_block7a[24..0].portbdataout[0..0]); 
END; 
--VALID FILE