www.pudn.com > 2-STM.rar > IO.src, change:2012-01-10,size:40708b


	; TASKING VX-toolset for TriCore: C compiler v3.4r1 Build 410 
	; Options: -f cc1124a -c99 --dep-file=.IO.o.d -Ctc1797 --core=tc1.3.1 --fpu-present -F -g --make-target=IO.o --no-tasking-sfr -t4 --language=-gcc,-volatile,+strings --default-near-size=0 -O2 --default-a1-size=0 --default-a0-size=0 --source --align=0 --compact-max-size=200 --switch=auto -o IO.src 
	; Module start 
	.name	"IO" 
 
	.extern	MAIN_vWriteWDTCON0 
	.weak	__libc_references 
	.extern	__libc_references 
	 
$FPU 
$TC131 
	 
	.sdecl	'.text.IO.IO_vInit',code,cluster('IO_vInit') 
	.sect	'.text.IO.IO_vInit' 
	.align	2 
	 
	.global	IO_vInit 
 
; ..\IO.c	     1  //**************************************************************************** 
; ..\IO.c	     2  // @Module        Parallel Ports 
; ..\IO.c	     3  // @Filename      IO.c 
; ..\IO.c	     4  // @Project       2-STM.dav 
; ..\IO.c	     5  //---------------------------------------------------------------------------- 
; ..\IO.c	     6  // @Controller    Infineon TC1797 
; ..\IO.c	     7  // 
; ..\IO.c	     8  // @Compiler      Tasking 3.1 
; ..\IO.c	     9  // 
; ..\IO.c	    10  // @Codegenerator 1.0 
; ..\IO.c	    11  // 
; ..\IO.c	    12  // @Description   This file contains functions that use the IO module. 
; ..\IO.c	    13  // 
; ..\IO.c	    14  //---------------------------------------------------------------------------- 
; ..\IO.c	    15  // @Date          2011-09-09 13:58:07 
; ..\IO.c	    16  // 
; ..\IO.c	    17  //**************************************************************************** 
; ..\IO.c	    18   
; ..\IO.c	    19  // USER CODE BEGIN (IO_General,1) 
; ..\IO.c	    20   
; ..\IO.c	    21  // USER CODE END 
; ..\IO.c	    22   
; ..\IO.c	    23   
; ..\IO.c	    24   
; ..\IO.c	    25  //**************************************************************************** 
; ..\IO.c	    26  // @Project Includes 
; ..\IO.c	    27  //**************************************************************************** 
; ..\IO.c	    28   
; ..\IO.c	    29  #include "MAIN.h" 
; ..\IO.c	    30   
; ..\IO.c	    31  // USER CODE BEGIN (IO_General,2) 
; ..\IO.c	    32   
; ..\IO.c	    33  // USER CODE END 
; ..\IO.c	    34   
; ..\IO.c	    35   
; ..\IO.c	    36  //**************************************************************************** 
; ..\IO.c	    37  // @Macros 
; ..\IO.c	    38  //**************************************************************************** 
; ..\IO.c	    39   
; ..\IO.c	    40  // USER CODE BEGIN (IO_General,3) 
; ..\IO.c	    41   
; ..\IO.c	    42  // USER CODE END 
; ..\IO.c	    43   
; ..\IO.c	    44   
; ..\IO.c	    45  //**************************************************************************** 
; ..\IO.c	    46  // @Defines 
; ..\IO.c	    47  //**************************************************************************** 
; ..\IO.c	    48   
; ..\IO.c	    49  // USER CODE BEGIN (IO_General,4) 
; ..\IO.c	    50   
; ..\IO.c	    51  // USER CODE END 
; ..\IO.c	    52   
; ..\IO.c	    53   
; ..\IO.c	    54  //**************************************************************************** 
; ..\IO.c	    55  // @Typedefs 
; ..\IO.c	    56  //**************************************************************************** 
; ..\IO.c	    57   
; ..\IO.c	    58  // USER CODE BEGIN (IO_General,5) 
; ..\IO.c	    59   
; ..\IO.c	    60  // USER CODE END 
; ..\IO.c	    61   
; ..\IO.c	    62   
; ..\IO.c	    63  //**************************************************************************** 
; ..\IO.c	    64  // @Imported Global Variables 
; ..\IO.c	    65  //**************************************************************************** 
; ..\IO.c	    66   
; ..\IO.c	    67  // USER CODE BEGIN (IO_General,6) 
; ..\IO.c	    68   
; ..\IO.c	    69  // USER CODE END 
; ..\IO.c	    70   
; ..\IO.c	    71   
; ..\IO.c	    72  //**************************************************************************** 
; ..\IO.c	    73  // @Global Variables 
; ..\IO.c	    74  //**************************************************************************** 
; ..\IO.c	    75   
; ..\IO.c	    76  // USER CODE BEGIN (IO_General,7) 
; ..\IO.c	    77   
; ..\IO.c	    78  // USER CODE END 
; ..\IO.c	    79   
; ..\IO.c	    80   
; ..\IO.c	    81  //**************************************************************************** 
; ..\IO.c	    82  // @External Prototypes 
; ..\IO.c	    83  //**************************************************************************** 
; ..\IO.c	    84   
; ..\IO.c	    85  // USER CODE BEGIN (IO_General,8) 
; ..\IO.c	    86   
; ..\IO.c	    87  // USER CODE END 
; ..\IO.c	    88   
; ..\IO.c	    89   
; ..\IO.c	    90  //**************************************************************************** 
; ..\IO.c	    91  // @Prototypes Of Local Functions 
; ..\IO.c	    92  //**************************************************************************** 
; ..\IO.c	    93   
; ..\IO.c	    94  // USER CODE BEGIN (IO_General,9) 
; ..\IO.c	    95   
; ..\IO.c	    96  // USER CODE END 
; ..\IO.c	    97   
; ..\IO.c	    98   
; ..\IO.c	    99  //**************************************************************************** 
; ..\IO.c	   100  // @Function      void IO_vInit(void)  
; ..\IO.c	   101  // 
; ..\IO.c	   102  //---------------------------------------------------------------------------- 
; ..\IO.c	   103  // @Description   This is the initialization function of the IO function  
; ..\IO.c	   104  //                library. It is assumed that the SFRs used by this library  
; ..\IO.c	   105  //                are in their reset state.  
; ..\IO.c	   106  //                Note: 
; ..\IO.c	   107  //                Alternate outputs are set in their own initialization  
; ..\IO.c	   108  //                function. 
; ..\IO.c	   109  // 
; ..\IO.c	   110  //---------------------------------------------------------------------------- 
; ..\IO.c	   111  // @Returnvalue   None 
; ..\IO.c	   112  // 
; ..\IO.c	   113  //---------------------------------------------------------------------------- 
; ..\IO.c	   114  // @Parameters    None 
; ..\IO.c	   115  // 
; ..\IO.c	   116  //---------------------------------------------------------------------------- 
; ..\IO.c	   117  // @Date          2011-09-09 
; ..\IO.c	   118  // 
; ..\IO.c	   119  //**************************************************************************** 
; ..\IO.c	   120   
; ..\IO.c	   121  // USER CODE BEGIN (IO_Function,1) 
; ..\IO.c	   122   
; ..\IO.c	   123  // USER CODE END 
; ..\IO.c	   124   
; ..\IO.c	   125  void IO_vInit(void) 
; Function IO_vInit 
.L20: 
IO_vInit:	.type	func 
 
; ..\IO.c	   126  { 
; ..\IO.c	   127    // USER CODE BEGIN (IO_Function,2) 
; ..\IO.c	   128   
; ..\IO.c	   129    // USER CODE END 
; ..\IO.c	   130   
; ..\IO.c	   131   
; ..\IO.c	   132    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   133    ///  Configuration of Port P0: 
; ..\IO.c	   134    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   135    ///  - no pin of port P0 is used 
; ..\IO.c	   136   
; ..\IO.c	   137    P0_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0000c04,d15 
.L45: 
 
; ..\IO.c	   138    MAIN_vResetENDINIT(); 
	lea	a12,0xf00005f0 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
	lea	a13,0xf00005f0 
.L2: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L2				; predicted taken 
.L46: 
 
; ..\IO.c	   139    P0_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0000c40,d15 
.L47: 
 
; ..\IO.c	   140    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L48: 
	call	MAIN_vWriteWDTCON0 
.L49: 
 
; ..\IO.c	   141    P0_IOCR0       =  0x20202020;  // load port control register 0 
	mov.u	d8,#8224 
	addih	d8,d8,#8224 
	st.w	0xf0000c10,d8 
.L50: 
 
; ..\IO.c	   142    P0_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0000c14,d8 
.L51: 
 
; ..\IO.c	   143    P0_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0000c18,d8 
.L52: 
 
; ..\IO.c	   144    P0_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf0000c1c,d8 
.L53: 
 
; ..\IO.c	   145   
; ..\IO.c	   146    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   147    ///  Configuration of Port P1: 
; ..\IO.c	   148    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   149    ///  - no pin of port P1 is used 
; ..\IO.c	   150   
; ..\IO.c	   151    P1_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0000d04,d15 
.L54: 
 
; ..\IO.c	   152    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L3: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L3				; predicted taken 
.L55: 
 
; ..\IO.c	   153    P1_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0000d40,d15 
.L56: 
 
; ..\IO.c	   154    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L57: 
	call	MAIN_vWriteWDTCON0 
.L58: 
 
; ..\IO.c	   155    P1_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0000d10,d8 
.L59: 
 
; ..\IO.c	   156    P1_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0000d14,d8 
.L60: 
 
; ..\IO.c	   157    P1_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0000d18,d8 
.L61: 
 
; ..\IO.c	   158    P1_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf0000d1c,d8 
.L62: 
 
; ..\IO.c	   159   
; ..\IO.c	   160    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   161    ///  Configuration of Port P2: 
; ..\IO.c	   162    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   163    ///  - no pin of port P2 is used 
; ..\IO.c	   164   
; ..\IO.c	   165    P2_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0000e04,d15 
.L63: 
 
; ..\IO.c	   166    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L4: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L4				; predicted taken 
.L64: 
 
; ..\IO.c	   167    P2_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0000e40,d15 
.L65: 
 
; ..\IO.c	   168    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L66: 
	call	MAIN_vWriteWDTCON0 
.L67: 
 
; ..\IO.c	   169    P2_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0000e10,d8 
.L68: 
 
; ..\IO.c	   170    P2_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0000e14,d8 
.L69: 
 
; ..\IO.c	   171    P2_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0000e18,d8 
.L70: 
 
; ..\IO.c	   172    P2_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf0000e1c,d8 
.L71: 
 
; ..\IO.c	   173   
; ..\IO.c	   174    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   175    ///  Configuration of Port P3: 
; ..\IO.c	   176    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   177    ///  P3.0: 
; ..\IO.c	   178    ///  - is used as general purpose output 
; ..\IO.c	   179    ///  - push/pull output is selected 
; ..\IO.c	   180    ///  - the pin status is low level 
; ..\IO.c	   181    ///  - output driver characteristic: medium driver 
; ..\IO.c	   182   
; ..\IO.c	   183    P3_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0000f04,d15 
.L72: 
 
; ..\IO.c	   184    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L5: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L5				; predicted taken 
.L73: 
 
; ..\IO.c	   185    P3_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0000f40,d15 
.L74: 
 
; ..\IO.c	   186    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L75: 
	call	MAIN_vWriteWDTCON0 
.L76: 
 
; ..\IO.c	   187    P3_IOCR0       =  0x20202080;  // load port control register 0 
	mov.u	d15,#8320 
	addih	d15,d15,#8224 
	st.w	0xf0000f10,d15 
.L77: 
 
; ..\IO.c	   188    P3_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0000f14,d8 
.L78: 
 
; ..\IO.c	   189    P3_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0000f18,d8 
.L79: 
 
; ..\IO.c	   190    P3_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf0000f1c,d8 
.L80: 
 
; ..\IO.c	   191   
; ..\IO.c	   192    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   193    ///  Configuration of Port P4: 
; ..\IO.c	   194    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   195    ///  - no pin of port P4 is used 
; ..\IO.c	   196   
; ..\IO.c	   197    P4_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001004,d15 
.L81: 
 
; ..\IO.c	   198    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L6: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L6				; predicted taken 
.L82: 
 
; ..\IO.c	   199    P4_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001040,d15 
.L83: 
 
; ..\IO.c	   200    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L84: 
	call	MAIN_vWriteWDTCON0 
.L85: 
 
; ..\IO.c	   201    P4_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0001010,d8 
.L86: 
 
; ..\IO.c	   202    P4_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0001014,d8 
.L87: 
 
; ..\IO.c	   203    P4_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0001018,d8 
.L88: 
 
; ..\IO.c	   204    P4_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf000101c,d8 
.L89: 
 
; ..\IO.c	   205   
; ..\IO.c	   206    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   207    ///  Configuration of Port P5: 
; ..\IO.c	   208    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   209    ///  - no pin of port P5 is used 
; ..\IO.c	   210   
; ..\IO.c	   211    P5_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001104,d15 
.L90: 
 
; ..\IO.c	   212    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L7: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L7				; predicted taken 
.L91: 
 
; ..\IO.c	   213    P5_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001140,d15 
.L92: 
 
; ..\IO.c	   214    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L93: 
	call	MAIN_vWriteWDTCON0 
.L94: 
 
; ..\IO.c	   215    P5_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0001110,d8 
.L95: 
 
; ..\IO.c	   216    P5_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0001114,d8 
.L96: 
 
; ..\IO.c	   217    P5_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0001118,d8 
.L97: 
 
; ..\IO.c	   218    P5_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf000111c,d8 
.L98: 
 
; ..\IO.c	   219   
; ..\IO.c	   220    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   221    ///  Configuration of Port P6: 
; ..\IO.c	   222    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   223    ///  - no pin of port P6 is used 
; ..\IO.c	   224   
; ..\IO.c	   225    P6_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001204,d15 
.L99: 
 
; ..\IO.c	   226    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L8: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L8				; predicted taken 
.L100: 
 
; ..\IO.c	   227    P6_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001240,d15 
.L101: 
 
; ..\IO.c	   228    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L102: 
	call	MAIN_vWriteWDTCON0 
.L103: 
 
; ..\IO.c	   229    P6_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0001210,d8 
.L104: 
 
; ..\IO.c	   230    P6_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0001214,d8 
.L105: 
 
; ..\IO.c	   231    P6_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0001218,d8 
.L106: 
 
; ..\IO.c	   232    P6_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf000121c,d8 
.L107: 
 
; ..\IO.c	   233   
; ..\IO.c	   234    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   235    ///  Configuration of Port P7: 
; ..\IO.c	   236    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   237    ///  - no pin of port P7 is used 
; ..\IO.c	   238   
; ..\IO.c	   239    P7_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001304,d15 
.L108: 
 
; ..\IO.c	   240    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L9: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L9				; predicted taken 
.L109: 
 
; ..\IO.c	   241    P7_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001340,d15 
.L110: 
 
; ..\IO.c	   242    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L111: 
	call	MAIN_vWriteWDTCON0 
.L112: 
 
; ..\IO.c	   243    P7_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0001310,d8 
.L113: 
 
; ..\IO.c	   244    P7_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0001314,d8 
.L114: 
 
; ..\IO.c	   245   
; ..\IO.c	   246    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   247    ///  Configuration of Port P8: 
; ..\IO.c	   248    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   249    ///  - no pin of port P8 is used 
; ..\IO.c	   250   
; ..\IO.c	   251    P8_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001404,d15 
.L115: 
 
; ..\IO.c	   252    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L10: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L10				; predicted taken 
.L116: 
 
; ..\IO.c	   253    P8_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001440,d15 
.L117: 
 
; ..\IO.c	   254    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L118: 
	call	MAIN_vWriteWDTCON0 
.L119: 
 
; ..\IO.c	   255    P8_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0001410,d8 
.L120: 
 
; ..\IO.c	   256    P8_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0001414,d8 
.L121: 
 
; ..\IO.c	   257   
; ..\IO.c	   258    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   259    ///  Configuration of Port P9: 
; ..\IO.c	   260    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   261    ///  - no pin of port P9 is used 
; ..\IO.c	   262   
; ..\IO.c	   263    P9_OMR         =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001504,d15 
.L122: 
 
; ..\IO.c	   264    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L11: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L11				; predicted taken 
.L123: 
 
; ..\IO.c	   265    P9_PDR         =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001540,d15 
.L124: 
 
; ..\IO.c	   266    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L125: 
	call	MAIN_vWriteWDTCON0 
.L126: 
 
; ..\IO.c	   267    P9_IOCR0       =  0x20202020;  // load port control register 0 
	st.w	0xf0001510,d8 
.L127: 
 
; ..\IO.c	   268    P9_IOCR4       =  0x20202020;  // load port control register 4 
	st.w	0xf0001514,d8 
.L128: 
 
; ..\IO.c	   269    P9_IOCR8       =  0x20202020;  // load port control register 8 
	st.w	0xf0001518,d8 
.L129: 
 
; ..\IO.c	   270    P9_IOCR12      =  0x20202020;  // load port control register 12 
	st.w	0xf000151c,d8 
.L130: 
 
; ..\IO.c	   271   
; ..\IO.c	   272    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   273    ///  Configuration of Port P10: 
; ..\IO.c	   274    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   275    ///  - no pin of port P10 is used 
; ..\IO.c	   276   
; ..\IO.c	   277    P10_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001604,d15 
.L131: 
 
; ..\IO.c	   278    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L12: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L12				; predicted taken 
.L132: 
 
; ..\IO.c	   279    P10_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001640,d15 
.L133: 
 
; ..\IO.c	   280    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L134: 
	call	MAIN_vWriteWDTCON0 
.L135: 
 
; ..\IO.c	   281    P10_IOCR0      =  0x20202020;  // load port control register 0 
	st.w	0xf0001610,d8 
.L136: 
 
; ..\IO.c	   282    P10_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	0xf0001614,d8 
.L137: 
 
; ..\IO.c	   283   
; ..\IO.c	   284    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   285    ///  Configuration of Port P11: 
; ..\IO.c	   286    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   287    ///  - no pin of port P11 is used 
; ..\IO.c	   288   
; ..\IO.c	   289    P11_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	0xf0001704,d15 
.L138: 
 
; ..\IO.c	   290    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L13: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L13				; predicted taken 
.L139: 
 
; ..\IO.c	   291    P11_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	st.w	0xf0001740,d15 
.L140: 
 
; ..\IO.c	   292    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L141: 
	call	MAIN_vWriteWDTCON0 
.L142: 
 
; ..\IO.c	   293    P11_IOCR0      =  0x20202020;  // load port control register 0 
	st.w	0xf0001710,d8 
.L143: 
 
; ..\IO.c	   294    P11_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	0xf0001714,d8 
.L144: 
 
; ..\IO.c	   295    P11_IOCR8      =  0x20202020;  // load port control register 8 
	st.w	0xf0001718,d8 
.L145: 
 
; ..\IO.c	   296    P11_IOCR12     =  0x20202020;  // load port control register 12 
	st.w	0xf000171c,d8 
.L146: 
 
; ..\IO.c	   297   
; ..\IO.c	   298    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   299    ///  Configuration of Port P12: 
; ..\IO.c	   300    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   301    ///  - no pin of port P12 is used 
; ..\IO.c	   302   
; ..\IO.c	   303    P12_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	movh.a	a15,#61488 
	st.w	[a15]4,d15 
.L147: 
 
; ..\IO.c	   304    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L14: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L14				; predicted taken 
.L148: 
 
; ..\IO.c	   305    P12_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300040),d15 
.L149: 
 
; ..\IO.c	   306    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L150: 
	call	MAIN_vWriteWDTCON0 
.L151: 
 
; ..\IO.c	   307    P12_IOCR0      =  0x20202020;  // load port control register 0 
	movh.a	a15,#61488 
	st.w	[a15]16,d8 
.L152: 
 
; ..\IO.c	   308    P12_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	[a15]20,d8 
.L153: 
 
; ..\IO.c	   309   
; ..\IO.c	   310    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   311    ///  Configuration of Port P13: 
; ..\IO.c	   312    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   313    ///  - no pin of port P13 is used 
; ..\IO.c	   314   
; ..\IO.c	   315    P13_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	[a15]@los(0xf0300104),d15 
.L154: 
 
; ..\IO.c	   316    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L15: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L15				; predicted taken 
.L155: 
 
; ..\IO.c	   317    P13_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300140),d15 
.L156: 
 
; ..\IO.c	   318    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L157: 
	call	MAIN_vWriteWDTCON0 
.L158: 
 
; ..\IO.c	   319    P13_IOCR0      =  0x20202020;  // load port control register 0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300110),d8 
.L159: 
 
; ..\IO.c	   320    P13_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	[a15]@los(0xf0300114),d8 
.L160: 
 
; ..\IO.c	   321    P13_IOCR8      =  0x20202020;  // load port control register 8 
	st.w	[a15]@los(0xf0300118),d8 
.L161: 
 
; ..\IO.c	   322    P13_IOCR12     =  0x20202020;  // load port control register 12 
	st.w	[a15]@los(0xf030011c),d8 
.L162: 
 
; ..\IO.c	   323   
; ..\IO.c	   324    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   325    ///  Configuration of Port P14: 
; ..\IO.c	   326    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   327    ///  - no pin of port P14 is used 
; ..\IO.c	   328   
; ..\IO.c	   329    P14_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	[a15]@los(0xf0300204),d15 
.L163: 
 
; ..\IO.c	   330    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L16: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L16				; predicted taken 
.L164: 
 
; ..\IO.c	   331    P14_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300240),d15 
.L165: 
 
; ..\IO.c	   332    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L166: 
	call	MAIN_vWriteWDTCON0 
.L167: 
 
; ..\IO.c	   333    P14_IOCR0      =  0x20202020;  // load port control register 0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300210),d8 
.L168: 
 
; ..\IO.c	   334    P14_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	[a15]@los(0xf0300214),d8 
.L169: 
 
; ..\IO.c	   335    P14_IOCR8      =  0x20202020;  // load port control register 8 
	st.w	[a15]@los(0xf0300218),d8 
.L170: 
 
; ..\IO.c	   336    P14_IOCR12     =  0x20202020;  // load port control register 12 
	st.w	[a15]@los(0xf030021c),d8 
.L171: 
 
; ..\IO.c	   337   
; ..\IO.c	   338    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   339    ///  Configuration of Port P15: 
; ..\IO.c	   340    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   341    ///  - no pin of port P15 is used 
; ..\IO.c	   342   
; ..\IO.c	   343    P15_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	[a15]@los(0xf0300304),d15 
.L172: 
 
; ..\IO.c	   344    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L17: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L17				; predicted taken 
.L173: 
 
; ..\IO.c	   345    P15_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300340),d15 
.L174: 
 
; ..\IO.c	   346    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L175: 
	call	MAIN_vWriteWDTCON0 
.L176: 
 
; ..\IO.c	   347    P15_IOCR0      =  0x20202020;  // load port control register 0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300310),d8 
.L177: 
 
; ..\IO.c	   348    P15_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	[a15]@los(0xf0300314),d8 
.L178: 
 
; ..\IO.c	   349    P15_IOCR8      =  0x20202020;  // load port control register 8 
	st.w	[a15]@los(0xf0300318),d8 
.L179: 
 
; ..\IO.c	   350    P15_IOCR12     =  0x20202020;  // load port control register 12 
	st.w	[a15]@los(0xf030031c),d8 
.L180: 
 
; ..\IO.c	   351   
; ..\IO.c	   352    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   353    ///  Configuration of Port P16: 
; ..\IO.c	   354    ///  ----------------------------------------------------------------------- 
; ..\IO.c	   355    ///  - no pin of port P16 is used 
; ..\IO.c	   356   
; ..\IO.c	   357    P16_OMR        =  0x00000000;  // load data output register 
	mov	d15,#0 
	st.w	[a15]@los(0xf0300404),d15 
.L181: 
 
; ..\IO.c	   358    MAIN_vResetENDINIT(); 
	ld.w	d15,[a12] 
	insert	d4,d15,#0,#0,#1 
	call	MAIN_vWriteWDTCON0 
.L18: 
	ld.bu	d15,[a13] 
	and	d15,#1 
	jne	d15,#0,.L18				; predicted taken 
.L182: 
 
; ..\IO.c	   359    P16_PDR        =  0x00000000;  // load pad driver mode register 
	mov	d15,#0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300440),d15 
.L183: 
 
; ..\IO.c	   360    MAIN_vSetENDINIT(); 
	ld.w	d15,[a12] 
	or	d4,d15,#1 
.L184: 
	call	MAIN_vWriteWDTCON0 
.L185: 
 
; ..\IO.c	   361    P16_IOCR0      =  0x20202020;  // load port control register 0 
	movh.a	a15,#61488 
	st.w	[a15]@los(0xf0300410),d8 
.L186: 
 
; ..\IO.c	   362    P16_IOCR4      =  0x20202020;  // load port control register 4 
	st.w	[a15]@los(0xf0300414),d8 
.L187: 
 
; ..\IO.c	   363   
; ..\IO.c	   364   
; ..\IO.c	   365    // USER CODE BEGIN (IO_Function,3) 
; ..\IO.c	   366   
; ..\IO.c	   367    // USER CODE END 
; ..\IO.c	   368   
; ..\IO.c	   369  } //  End of function IO_vInit 
	ret 
.L30: 
	.calls	'IO_vInit','',0 
	 
__IO_vInit_function_end: 
	.size	IO_vInit,__IO_vInit_function_end-IO_vInit 
.L29: 
	; End of function 
	 
	 
	.calls	'IO_vInit','MAIN_vWriteWDTCON0' 
	 
	.sdecl	'.debug_info',debug 
	.sect	'.debug_info' 
.L22: 
	.word	830 
	.half	2 
	.word	.L23 
	.byte	4 
.L21: 
	.byte	1 
	.byte	'..\\IO.c',0 
	.byte	'TASKING VX-toolset for TriCore: C compiler',0 
	.byte	'E:\\1-EVM Demo\\4.4-TC1797_Qianqin_v1.0\\TC1797 Demo Code\\2-STM\\Debug\\',0,12,1 
	.word	.L24 
	.byte	2 
	.byte	'MAIN_vWriteWDTCON0',0,1,139,1,6,1,1,1,1,3 
	.byte	'uwValue',0,1,139,1,31 
	.word	.L31-.L22 
	.byte	0 
.L31: 
	.byte	4 
	.byte	'unsigned int',0,4,7,5 
	.byte	'__size_t',0,2,1,1 
	.word	183 
	.byte	5 
	.byte	'__codeptr',0,2,1,1 
	.word	.L32-.L22 
.L32: 
	.byte	6 
	.word	.L33-.L22 
.L33: 
	.byte	7,1,5 
	.byte	'uword',0,1,73,24 
	.word	183 
	.byte	5 
	.byte	'T_Reg32',0,1,110,4 
	.word	.L34-.L22 
.L34: 
	.byte	8 
	.word	.L35-.L22 
.L35: 
	.byte	9,1,76,18,4,10 
	.byte	'bit0',0,1 
	.word	.L36-.L22 
	.byte	1,7,2,35,0,10 
	.byte	'bit1',0,1 
	.word	.L36-.L22 
	.byte	1,6,2,35,0,10 
	.byte	'bit2',0,1 
	.word	.L36-.L22 
	.byte	1,5,2,35,0,10 
	.byte	'bit3',0,1 
	.word	.L36-.L22 
	.byte	1,4,2,35,0,10 
	.byte	'bit4',0,1 
	.word	.L36-.L22 
	.byte	1,3,2,35,0,10 
	.byte	'bit5',0,1 
	.word	.L36-.L22 
	.byte	1,2,2,35,0,10 
	.byte	'bit6',0,1 
	.word	.L36-.L22 
	.byte	1,1,2,35,0,10 
	.byte	'bit7',0,1 
	.word	.L36-.L22 
	.byte	1,0,2,35,0,10 
	.byte	'bit8',0,1 
	.word	.L36-.L22 
	.byte	1,7,2,35,1,10 
	.byte	'bit9',0,1 
	.word	.L36-.L22 
	.byte	1,6,2,35,1,10 
	.byte	'bit10',0,1 
	.word	.L36-.L22 
	.byte	1,5,2,35,1,10 
	.byte	'bit11',0,1 
	.word	.L36-.L22 
	.byte	1,4,2,35,1,10 
	.byte	'bit12',0,1 
	.word	.L36-.L22 
	.byte	1,3,2,35,1,10 
	.byte	'bit13',0,1 
	.word	.L36-.L22 
	.byte	1,2,2,35,1,10 
	.byte	'bit14',0,1 
	.word	.L36-.L22 
	.byte	1,1,2,35,1,10 
	.byte	'bit15',0,1 
	.word	.L36-.L22 
	.byte	1,0,2,35,1,10 
	.byte	'bit16',0,1 
	.word	.L36-.L22 
	.byte	1,7,2,35,2,10 
	.byte	'bit17',0,1 
	.word	.L36-.L22 
	.byte	1,6,2,35,2,10 
	.byte	'bit18',0,1 
	.word	.L36-.L22 
	.byte	1,5,2,35,2,10 
	.byte	'bit19',0,1 
	.word	.L36-.L22 
	.byte	1,4,2,35,2,10 
	.byte	'bit20',0,1 
	.word	.L36-.L22 
	.byte	1,3,2,35,2,10 
	.byte	'bit21',0,1 
	.word	.L36-.L22 
	.byte	1,2,2,35,2,10 
	.byte	'bit22',0,1 
	.word	.L36-.L22 
	.byte	1,1,2,35,2,10 
	.byte	'bit23',0,1 
	.word	.L36-.L22 
	.byte	1,0,2,35,2,10 
	.byte	'bit24',0,1 
	.word	.L36-.L22 
	.byte	1,7,2,35,3,10 
	.byte	'bit25',0,1 
	.word	.L36-.L22 
	.byte	1,6,2,35,3,10 
	.byte	'bit26',0,1 
	.word	.L36-.L22 
	.byte	1,5,2,35,3,10 
	.byte	'bit27',0,1 
	.word	.L36-.L22 
	.byte	1,4,2,35,3,10 
	.byte	'bit28',0,1 
	.word	.L36-.L22 
	.byte	1,3,2,35,3,10 
	.byte	'bit29',0,1 
	.word	.L36-.L22 
	.byte	1,2,2,35,3,10 
	.byte	'bit30',0,1 
	.word	.L36-.L22 
	.byte	1,1,2,35,3,10 
	.byte	'bit31',0,1 
	.word	.L36-.L22 
	.byte	1,0,2,35,3,0 
.L36: 
	.byte	4 
	.byte	'unsigned char',0,1,8,0 
	.sdecl	'.debug_abbrev',debug 
	.sect	'.debug_abbrev' 
.L23: 
	.byte	1,17,1,3,8,37,8,27,8,19,15,128,70,12,16,6,0,0,2,46,1,3,8,58,15,59,15,57,15,54,15,39,12,63,12,60,12,0,0 
	.byte	3,5,0,3,8,58,15,59,15,57,15,73,19,0,0,4,36,0,3,8,11,15,62,15,0,0,5,22,0,3,8,58,15,59,15,57,15,73,19,0 
	.byte	0,6,15,0,73,19,0,0,7,21,0,54,15,0,0,8,53,0,73,19,0,0,9,19,1,58,15,59,15,57,15,11,15,0,0,10,13,0,3,8,11 
	.byte	15,73,19,13,15,12,15,56,9,0,0,0 
	.sdecl	'.debug_line',debug 
	.sect	'.debug_line' 
.L24: 
	.word	.L38-.L37 
.L37: 
	.half	2 
	.word	.L40-.L39 
.L39: 
	.byte	2,1,-4,9,10,0,1,1,1,1,0,0,0,1,0 
	.byte	'..\\MAIN.h',0,0,0,0 
	.byte	'..\\IO.c',0,0,0,0,0 
.L40: 
.L38: 
	.sdecl	'.debug_info',debug,cluster('IO_vInit') 
	.sect	'.debug_info' 
.L25: 
	.word	181 
	.half	2 
	.word	.L26 
	.byte	4,1 
	.byte	'..\\IO.c',0 
	.byte	'TASKING VX-toolset for TriCore: C compiler',0 
	.byte	'E:\\1-EVM Demo\\4.4-TC1797_Qianqin_v1.0\\TC1797 Demo Code\\2-STM\\Debug\\',0,12,1 
	.word	.L28,.L27 
	.byte	2 
	.word	.L21 
	.byte	3 
	.byte	'IO_vInit',0,1,125,6,1,1,1 
	.word	.L20,.L30,.L19 
	.byte	4 
	.word	.L20,.L30 
	.byte	0,0 
	.sdecl	'.debug_abbrev',debug,cluster('IO_vInit') 
	.sect	'.debug_abbrev' 
.L26: 
	.byte	1,17,1,3,8,37,8,27,8,19,15,128,70,12,85,6,16,6,0,0,2,61,0,24,16,0,0,3,46,1,3,8,58,15,59,15,57,15,54,15 
	.byte	39,12,63,12,17,1,18,1,64,6,0,0,4,11,0,17,1,18,1,0,0,0 
	.sdecl	'.debug_line',debug,cluster('IO_vInit') 
	.sect	'.debug_line' 
.L27: 
	.word	.L42-.L41 
.L41: 
	.half	2 
	.word	.L44-.L43 
.L43: 
	.byte	2,1,-4,9,10,0,1,1,1,1,0,0,0,1,0 
	.byte	'..\\IO.c',0,0,0,0,0 
.L44: 
	.byte	5,31,7,0,5,2 
	.word	.L20 
	.byte	3,136,1,1,5,3,9 
	.half	.L45-.L20 
	.byte	3,1,1,5,31,9 
	.half	.L46-.L45 
	.byte	3,1,1,5,3,9 
	.half	.L47-.L46 
	.byte	3,1,1,5,21,9 
	.half	.L48-.L47 
	.byte	1,5,31,9 
	.half	.L49-.L48 
	.byte	3,1,1,9 
	.half	.L50-.L49 
	.byte	3,1,1,9 
	.half	.L51-.L50 
	.byte	3,1,1,9 
	.half	.L52-.L51 
	.byte	3,1,1,9 
	.half	.L53-.L52 
	.byte	3,7,1,5,3,9 
	.half	.L54-.L53 
	.byte	3,1,1,5,31,9 
	.half	.L55-.L54 
	.byte	3,1,1,5,3,9 
	.half	.L56-.L55 
	.byte	3,1,1,5,21,9 
	.half	.L57-.L56 
	.byte	1,5,31,9 
	.half	.L58-.L57 
	.byte	3,1,1,9 
	.half	.L59-.L58 
	.byte	3,1,1,9 
	.half	.L60-.L59 
	.byte	3,1,1,9 
	.half	.L61-.L60 
	.byte	3,1,1,9 
	.half	.L62-.L61 
	.byte	3,7,1,5,3,9 
	.half	.L63-.L62 
	.byte	3,1,1,5,31,9 
	.half	.L64-.L63 
	.byte	3,1,1,5,3,9 
	.half	.L65-.L64 
	.byte	3,1,1,5,21,9 
	.half	.L66-.L65 
	.byte	1,5,31,9 
	.half	.L67-.L66 
	.byte	3,1,1,9 
	.half	.L68-.L67 
	.byte	3,1,1,9 
	.half	.L69-.L68 
	.byte	3,1,1,9 
	.half	.L70-.L69 
	.byte	3,1,1,9 
	.half	.L71-.L70 
	.byte	3,11,1,5,3,9 
	.half	.L72-.L71 
	.byte	3,1,1,5,31,9 
	.half	.L73-.L72 
	.byte	3,1,1,5,3,9 
	.half	.L74-.L73 
	.byte	3,1,1,5,21,9 
	.half	.L75-.L74 
	.byte	1,5,31,9 
	.half	.L76-.L75 
	.byte	3,1,1,9 
	.half	.L77-.L76 
	.byte	3,1,1,9 
	.half	.L78-.L77 
	.byte	3,1,1,9 
	.half	.L79-.L78 
	.byte	3,1,1,9 
	.half	.L80-.L79 
	.byte	3,7,1,5,3,9 
	.half	.L81-.L80 
	.byte	3,1,1,5,31,9 
	.half	.L82-.L81 
	.byte	3,1,1,5,3,9 
	.half	.L83-.L82 
	.byte	3,1,1,5,21,9 
	.half	.L84-.L83 
	.byte	1,5,31,9 
	.half	.L85-.L84 
	.byte	3,1,1,9 
	.half	.L86-.L85 
	.byte	3,1,1,9 
	.half	.L87-.L86 
	.byte	3,1,1,9 
	.half	.L88-.L87 
	.byte	3,1,1,9 
	.half	.L89-.L88 
	.byte	3,7,1,5,3,9 
	.half	.L90-.L89 
	.byte	3,1,1,5,31,9 
	.half	.L91-.L90 
	.byte	3,1,1,5,3,9 
	.half	.L92-.L91 
	.byte	3,1,1,5,21,9 
	.half	.L93-.L92 
	.byte	1,5,31,9 
	.half	.L94-.L93 
	.byte	3,1,1,9 
	.half	.L95-.L94 
	.byte	3,1,1,9 
	.half	.L96-.L95 
	.byte	3,1,1,9 
	.half	.L97-.L96 
	.byte	3,1,1,9 
	.half	.L98-.L97 
	.byte	3,7,1,5,3,9 
	.half	.L99-.L98 
	.byte	3,1,1,5,31,9 
	.half	.L100-.L99 
	.byte	3,1,1,5,3,9 
	.half	.L101-.L100 
	.byte	3,1,1,5,21,9 
	.half	.L102-.L101 
	.byte	1,5,31,9 
	.half	.L103-.L102 
	.byte	3,1,1,9 
	.half	.L104-.L103 
	.byte	3,1,1,9 
	.half	.L105-.L104 
	.byte	3,1,1,9 
	.half	.L106-.L105 
	.byte	3,1,1,9 
	.half	.L107-.L106 
	.byte	3,7,1,5,3,9 
	.half	.L108-.L107 
	.byte	3,1,1,5,31,9 
	.half	.L109-.L108 
	.byte	3,1,1,5,3,9 
	.half	.L110-.L109 
	.byte	3,1,1,5,21,9 
	.half	.L111-.L110 
	.byte	1,5,31,9 
	.half	.L112-.L111 
	.byte	3,1,1,9 
	.half	.L113-.L112 
	.byte	3,1,1,9 
	.half	.L114-.L113 
	.byte	3,7,1,5,3,9 
	.half	.L115-.L114 
	.byte	3,1,1,5,31,9 
	.half	.L116-.L115 
	.byte	3,1,1,5,3,9 
	.half	.L117-.L116 
	.byte	3,1,1,5,21,9 
	.half	.L118-.L117 
	.byte	1,5,31,9 
	.half	.L119-.L118 
	.byte	3,1,1,9 
	.half	.L120-.L119 
	.byte	3,1,1,9 
	.half	.L121-.L120 
	.byte	3,7,1,5,3,9 
	.half	.L122-.L121 
	.byte	3,1,1,5,31,9 
	.half	.L123-.L122 
	.byte	3,1,1,5,3,9 
	.half	.L124-.L123 
	.byte	3,1,1,5,21,9 
	.half	.L125-.L124 
	.byte	1,5,31,9 
	.half	.L126-.L125 
	.byte	3,1,1,9 
	.half	.L127-.L126 
	.byte	3,1,1,9 
	.half	.L128-.L127 
	.byte	3,1,1,9 
	.half	.L129-.L128 
	.byte	3,1,1,9 
	.half	.L130-.L129 
	.byte	3,7,1,5,3,9 
	.half	.L131-.L130 
	.byte	3,1,1,5,31,9 
	.half	.L132-.L131 
	.byte	3,1,1,5,3,9 
	.half	.L133-.L132 
	.byte	3,1,1,5,21,9 
	.half	.L134-.L133 
	.byte	1,5,31,9 
	.half	.L135-.L134 
	.byte	3,1,1,9 
	.half	.L136-.L135 
	.byte	3,1,1,9 
	.half	.L137-.L136 
	.byte	3,7,1,5,3,9 
	.half	.L138-.L137 
	.byte	3,1,1,5,31,9 
	.half	.L139-.L138 
	.byte	3,1,1,5,3,9 
	.half	.L140-.L139 
	.byte	3,1,1,5,21,9 
	.half	.L141-.L140 
	.byte	1,5,31,9 
	.half	.L142-.L141 
	.byte	3,1,1,9 
	.half	.L143-.L142 
	.byte	3,1,1,9 
	.half	.L144-.L143 
	.byte	3,1,1,9 
	.half	.L145-.L144 
	.byte	3,1,1,9 
	.half	.L146-.L145 
	.byte	3,7,1,5,3,9 
	.half	.L147-.L146 
	.byte	3,1,1,5,31,9 
	.half	.L148-.L147 
	.byte	3,1,1,5,3,9 
	.half	.L149-.L148 
	.byte	3,1,1,5,21,9 
	.half	.L150-.L149 
	.byte	1,5,31,9 
	.half	.L151-.L150 
	.byte	3,1,1,9 
	.half	.L152-.L151 
	.byte	3,1,1,9 
	.half	.L153-.L152 
	.byte	3,7,1,5,3,9 
	.half	.L154-.L153 
	.byte	3,1,1,5,31,9 
	.half	.L155-.L154 
	.byte	3,1,1,5,3,9 
	.half	.L156-.L155 
	.byte	3,1,1,5,21,9 
	.half	.L157-.L156 
	.byte	1,5,31,9 
	.half	.L158-.L157 
	.byte	3,1,1,9 
	.half	.L159-.L158 
	.byte	3,1,1,9 
	.half	.L160-.L159 
	.byte	3,1,1,9 
	.half	.L161-.L160 
	.byte	3,1,1,9 
	.half	.L162-.L161 
	.byte	3,7,1,5,3,9 
	.half	.L163-.L162 
	.byte	3,1,1,5,31,9 
	.half	.L164-.L163 
	.byte	3,1,1,5,3,9 
	.half	.L165-.L164 
	.byte	3,1,1,5,21,9 
	.half	.L166-.L165 
	.byte	1,5,31,9 
	.half	.L167-.L166 
	.byte	3,1,1,9 
	.half	.L168-.L167 
	.byte	3,1,1,9 
	.half	.L169-.L168 
	.byte	3,1,1,9 
	.half	.L170-.L169 
	.byte	3,1,1,9 
	.half	.L171-.L170 
	.byte	3,7,1,5,3,9 
	.half	.L172-.L171 
	.byte	3,1,1,5,31,9 
	.half	.L173-.L172 
	.byte	3,1,1,5,3,9 
	.half	.L174-.L173 
	.byte	3,1,1,5,21,9 
	.half	.L175-.L174 
	.byte	1,5,31,9 
	.half	.L176-.L175 
	.byte	3,1,1,9 
	.half	.L177-.L176 
	.byte	3,1,1,9 
	.half	.L178-.L177 
	.byte	3,1,1,9 
	.half	.L179-.L178 
	.byte	3,1,1,9 
	.half	.L180-.L179 
	.byte	3,7,1,5,3,9 
	.half	.L181-.L180 
	.byte	3,1,1,5,31,9 
	.half	.L182-.L181 
	.byte	3,1,1,5,3,9 
	.half	.L183-.L182 
	.byte	3,1,1,5,21,9 
	.half	.L184-.L183 
	.byte	1,5,31,9 
	.half	.L185-.L184 
	.byte	3,1,1,9 
	.half	.L186-.L185 
	.byte	3,1,1,5,1,9 
	.half	.L187-.L186 
	.byte	3,7,1,7,9 
	.half	.L29-.L187 
	.byte	0,1,1 
.L42: 
	.sdecl	'.debug_ranges',debug,cluster('IO_vInit') 
	.sect	'.debug_ranges' 
.L28: 
	.word	-1,.L20,0,.L29-.L20,0,0 
	.sdecl	'.debug_loc',debug,cluster('IO_vInit') 
	.sect	'.debug_loc' 
.L19: 
	.word	-1,.L20,.L20-.L20,.L30-.L20 
	.half	2 
	.byte	138,0 
	.word	0,0 
	.sdecl	'.debug_frame',debug 
	.sect	'.debug_frame' 
.L188: 
	.word	48 
	.word	-1 
	.byte	1,0,2,1,0x1b,12,26,0,8,26,8,27,8,28,8,29,8,30,8,31,8,16,8,17,8,24,8,25,8,32,8,33,8,34,8,35,8,36,8,37,8 
	.byte	38,8,39 
	.sdecl	'.debug_frame',debug,cluster('IO_vInit') 
	.sect	'.debug_frame' 
	.word	12 
	.word	.L188,.L20,.L30-.L20 
 
; ..\IO.c	   370   
; ..\IO.c	   371   
; ..\IO.c	   372   
; ..\IO.c	   373   
; ..\IO.c	   374  // USER CODE BEGIN (IO_General,10) 
; ..\IO.c	   375   
; ..\IO.c	   376  // USER CODE END 
; ..\IO.c	   377   
 
	; Module end