www.pudn.com > wcdma_simulink.rar > koe_ul_opne.mdl
Model {
Name "koe_ul_opne"
Version 3.00
SimParamPage "Solver"
SampleTimeColors off
InvariantConstants off
WideVectorLines off
ShowLineWidths on
ShowPortDataTypes off
StartTime "0.0"
StopTime "10.0"
SolverMode "Auto"
Solver "ode45"
RelTol "1e-3"
AbsTol "auto"
Refine "1"
MaxStep "auto"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Matrix"
LimitMaxRows off
MaxRows "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
IntegerOverflowMsg "warning"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
SignalLabelMismatchMsg "none"
ConsistencyChecking "off"
ZeroCross on
SimulationMode "normal"
BlockDataTips on
BlockParametersDataTip on
BlockAttributesDataTip off
BlockPortWidthsDataTip off
BlockDescriptionStringDataTip off
BlockMaskParametersDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
OptimizeBlockIOStorage on
BufferReuse on
BooleanDataType off
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
Created "Thu Jun 24 19:00:42 1999"
Creator "maarit"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%"
LastModifiedBy "maarit"
ModifiedDateFormat "%"
LastModifiedDate "Thu Jun 24 20:27:14 1999"
ModelVersionFormat "1.%"
ConfigurationManager "none"
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "koe_ul_opne"
Location [84, 270, 584, 530]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
ReportName "simulink-default.rpt"
Block {
BlockType SubSystem
Name "ul_empty"
Ports [0, 0, 0, 0, 0]
Position [113, 45, 390, 206]
Orientation "left"
ShowPortLabels on
MaskPromptString "TX channel Type|Channel coding |Coding ratio "
" |Spreading code length for data channel|Spreading code length for contro"
"l channel|Inter frame interleaver |Number of frames for inter frame interleav"
"er|Number of columns for inter frame interleaver |Intra frame interleaver (on"
" or off)"
MaskStyleString "popup(Dedicated Physical data channel + control"
" channel),popup(Convolutional coding|Turbo),popup(2|3),popup(4|8|16|32|64|128"
"|256),popup(4|8|16|32|64|128|256),popup(block interleaver|multistage interlea"
"ver),edit,edit,checkbox"
MaskTunableValueString "on,on,on,on,on,on,on,on,on"
MaskCallbackString "||||||||"
MaskEnableString "on,on,on,on,on,on,on,on,on"
MaskVisibilityString "on,on,on,on,on,on,on,on,on"
MaskVariables "tx_ch=@1;cType=@2;Kin=@3;nD=@4;nC=@5;Inter_int_"
"mode=@6;nFrames=@7;cols=@8;Intra_int_flag=@9;"
MaskInitialization "ndc=2^(nD+1);ncc=2^(nC+1);\n % if you wa"
"nt to specify which code is used define ndc=[ndc index]\n[sizes,crc,chCode,CD"
",CC,control]=ul_start(ndc,ncc,cType,Kin,nFrames,tx_ch);\ninput_block_size=siz"
"es(1);N=input_block_size;bits_in_frame=sizes(2);\nnFrames=sizes(3); nSlot=siz"
"es(5); chips_in_slot=sizes(6); nCRC=crc(1);crc_poly=crc(2);\ncType=chCode(1);"
"K=chCode(2); nTail=chCode(3);ch_poly=[chCode(4:6)];\nnPilot=control(1);TPC=co"
"ntrol(2);TFI=control(3);"
MaskDisplay "disp('EMPTY SUBSYSTEM MASK\\n\\nUPLINK\\n\\nTra"
"nsportChannel\\n\\n\\n\\n\\n1 - Decicated physical data channel and contorl c"
"hannel\\n')\ndisp(tx_ch)"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
MaskValueString "Dedicated Physical data channel + control chann"
"el|Convolutional coding|3|256|256|block interleaver|1|1|off"
System {
Name "ul_empty"
Location [31, 58, 1270, 983]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Reference
Name "Add CRC2"
Ports [1, 1, 0, 0, 0]
Position [85, 102, 175, 158]
ShowName off
FontName "helvetica"
SourceBlock "utra_lib/Channel coding block/dl_TX_channel"
"_coding/Add CRC2"
SourceType ""
N "N"
nCRC "nCRC"
crc_poly "crc_poly"
nFrames "nFrames"
}
Block {
BlockType Reference
Name "Buffer"
Ports [2, 2, 0, 0, 0]
Position [925, 779, 1020, 861]
Orientation "left"
NamePlacement "alternate"
SourceBlock "utra_lib/Modulation blocks/Buffer"
SourceType ""
nIn "2*bits_in_frame/nSlot"
nOut "bits_in_frame"
nSlot "nSlot"
}
Block {
BlockType Reference
Name "Channel estimator"
Ports [2, 3, 0, 0, 0]
Position [1095, 510, 1175, 580]
Orientation "down"
ForegroundColor "blue"
NamePlacement "alternate"
ShowName off
SourceBlock "utra_lib/Channel models/Channel estimator"
SourceType ""
threshold "0.05"
nSlot "nSlot"
}
Block {
BlockType Constant
Name "Constant"
Position [95, 164, 165, 196]
ShowName off
Value "N+nCRC"
}
Block {
BlockType Reference
Name "Delayed ber calculation"
Ports [2, 1, 0, 0, 0]
Position [140, 377, 305, 473]
SourceBlock "utra_lib/Test functions/Delayed ber calcula"
"tion"
SourceType ""
N "input_block_size"
nFrames "nFrames"
}
Block {
BlockType Display
Name "Display1"
Ports [1, 0, 0, 0, 0]
Position [370, 383, 460, 437]
ShowName off
Format "short"
Decimation "1"
Floating off
SampleTime "-1"
}
Block {
BlockType Reference
Name "Rate Matching"
Ports [1, 1, 0, 0, 0]
Position [430, 129, 515, 181]
SourceBlock "utra_lib/Channel coding block/dl_TX_channel"
"_coding/Rate Matching"
SourceType ""
r_in "K*(N+nCRC)+nTail"
r_out "nFrames*bits_in_frame"
punk "0.2"
nFrames "nFrames"
}
Block {
BlockType ToWorkspace
Name "To Workspace23"
Position [370, 460, 430, 490]
ShowName off
VariableName "ber"
Buffer "inf"
Decimation "1"
SampleTime "nFrames"
SaveFormat "Matrix"
}
Block {
BlockType ToWorkspace
Name "To Workspace24"
Position [15, 842, 45, 878]
Orientation "left"
NamePlacement "alternate"
ShowName off
VariableName "fer"
Buffer "inf"
Decimation "1"
SampleTime "nFrames"
SaveFormat "Matrix"
}
Block {
BlockType Reference
Name "ch_coding"
Ports [2, 2, 0, 0, 0]
Position [205, 107, 345, 203]
ForegroundColor "blue"
SourceBlock "utra_lib/Channel coding block/dl_TX_channel"
"_coding/ch_coding"
SourceType "wcdma"
N_chcode "N+nCRC"
cType "cType"
K "K"
nTail "nTail"
poly "ch_poly"
nFrames "nFrames"
}
Block {
BlockType Reference
Name "ch_decoding"
Ports [2, 2, 0, 0, 0]
Position [230, 768, 370, 892]
Orientation "left"
ForegroundColor "green"
NamePlacement "alternate"
FontName "helvetica"
FontSize 12
FontWeight "bold"
SourceBlock "utra_lib/Channel coding block/dl_RX_channel"
"_decoding/ch_decoding"
SourceType "wcdma"
N_chdecode "(nCRC+N)*K+nTail"
cType "cType"
K "K"
nTail "nTail"
poly "ch_poly"
nFrames "nFrames"
sp0 "[1 0]"
sp1 "[ 0 1]"
}
Block {
BlockType Reference
Name "channel2"
Ports [2, 4, 0, 0, 0]
Position [1054, 320, 1216, 485]
Orientation "down"
ForegroundColor "blue"
NamePlacement "alternate"
ShowName off
FontName "helvetica"
FontWeight "bold"
SourceBlock "utra_lib/Channel models/channel2"
SourceType ""
N "chips_in_slot"
nSlot "nSlot"
RM "[0.9 0 0.1]"
DM "[0 1 2]"
HP "1"
snr "0"
P "0"
nCode "max(ncc,ndc)"
in_type "int"
}
Block {
BlockType Reference
Name "control channel bits"
Ports [0, 1, 0, 0, 0]
Position [705, 223, 865, 387]
FontName "helvetica"
FontSize 12
SourceBlock "utra_lib/Modulation blocks/ul_TX_modulatio"
"n/control channel bits"
SourceType ""
nPilot "nPilot"
nPower "TPC"
nTFI "TFI"
}
Block {
BlockType Reference
Name "data source 01 ..10"
Ports [0, 1, 0, 0, 0]
Position [12, 25, 98, 65]
Orientation "down"
NamePlacement "alternate"
ShowName off
SourceBlock "utra_lib/Source blocks/data source 01 ..10"
SourceType "koe"
nFrames "nFrames"
N "N"
}
Block {
BlockType Reference
Name "inter_deinterleaving"
Ports [2, 2, 0, 0, 0]
Position [550, 769, 695, 891]
Orientation "left"
ForegroundColor "blue"
NamePlacement "alternate"
SourceBlock "utra_lib/Modulation blocks/dl_RX_demodulat"
"ion/inter_deinterleaving"
SourceType ""
Int_mode "Inter_int_mode"
bits_in_frame "bits_in_frame"
nFrames "nFrames"
cols "cols"
}
Block {
BlockType Reference
Name "inter_interleaving"
Ports [1, 1, 0, 0, 0]
Position [555, 109, 685, 201]
ForegroundColor "blue"
SourceBlock "utra_lib/Modulation blocks/dl_TX_modulatio"
"n/inter_interleaving"
SourceType ""
Int_mode "Inter_int_mode"
bits_in_frame "bits_in_frame"
nFrames "nFrames"
cols "cols"
}
Block {
BlockType Reference
Name "intra_deinterleaving"
Ports [2, 2, 0, 0, 0]
Position [735, 771, 885, 889]
Orientation "left"
ForegroundColor "blue"
NamePlacement "alternate"
SourceBlock "utra_lib/Modulation blocks/dl_RX_demodulat"
"ion/intra_deinterleaving"
SourceType ""
Int_mode "Intra_int_flag"
bits_in_frame "bits_in_frame"
nFrames "nFrames"
}
Block {
BlockType Reference
Name "intra_interleaving"
Ports [1, 1, 0, 0, 0]
Position [725, 109, 855, 201]
ForegroundColor "blue"
SourceBlock "utra_lib/Modulation blocks/dl_TX_modulatio"
"n/intra_interleaving"
SourceType ""
Int_mode "Intra_int_flag"
bits_in_frame "bits_in_frame"
nFrames "nFrames"
nSlots "nSlot"
}
Block {
BlockType Reference
Name "rate_dematching"
Ports [2, 2, 0, 0, 0]
Position [420, 771, 520, 889]
Orientation "left"
ForegroundColor "green"
NamePlacement "alternate"
FontName "helvetica"
FontSize 12
FontWeight "bold"
SourceBlock "utra_lib/Channel coding block/dl_RX_channel"
"_decoding/rate_dematching"
SourceType ""
dr_in "nFrames*bits_in_frame"
dr_out "K*(N+nCRC)+nTail"
punk "0.2"
nFrames "nFrames"
}
Block {
BlockType Reference
Name "remove CRC"
Ports [2, 2, 0, 0, 0]
Position [65, 768, 200, 892]
Orientation "left"
ForegroundColor "green"
NamePlacement "alternate"
FontName "helvetica"
FontSize 12
FontWeight "bold"
SourceBlock "utra_lib/Channel coding block/dl_RX_channel"
"_decoding/remove CRC"
SourceType ""
nReCRC "N+nCRC"
nCRC "nCRC"
crc_poly "crc_poly"
nFrames "nFrames"
}
Block {
BlockType Reference
Name "spreading"
Ports [1, 1, 0, 0, 0]
Position [895, 122, 1030, 188]
SourceBlock "utra_lib/Modulation blocks/spreading"
SourceType ""
N "bits_in_frame/nSlot"
C "CD"
nSlot "nSlot"
}
Block {
BlockType Reference
Name "spreading1"
Ports [1, 1, 0, 0, 0]
Position [905, 272, 1045, 338]
SourceBlock "utra_lib/Modulation blocks/spreading"
SourceType ""
N "sum(control)"
C "CC"
nSlot "nSlot"
}
Block {
BlockType Mux
Name "tail_mux"
Ports [2, 1, 0, 0, 0]
Position [390, 105, 395, 205]
ShowName off
FontName "helvetica"
FontSize 12
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Reference
Name "ul_rake"
Ports [5, 4, 0, 0, 0]
Position [1056, 605, 1214, 795]
Orientation "down"
NamePlacement "alternate"
FontName "helvetica"
FontSize 12
SourceBlock "utra_lib/Receivers/ul_rake"
SourceType ""
N_rake "chips_in_slot"
nSlot "nSlot"
nPilot "nPilot"
th "0.1"
nFin "1"
CD "CD"
CC "CC"
}
Line {
SrcBlock "intra_interleaving"
SrcPort 1
DstBlock "spreading"
DstPort 1
}
Line {
SrcBlock "Rate Matching"
SrcPort 1
DstBlock "inter_interleaving"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
DstBlock "ch_coding"
DstPort 2
}
Line {
SrcBlock "Add CRC2"
SrcPort 1
DstBlock "ch_coding"
DstPort 1
}
Line {
SrcBlock "ch_coding"
SrcPort 1
DstBlock "tail_mux"
DstPort 1
}
Line {
SrcBlock "ch_coding"
SrcPort 2
DstBlock "tail_mux"
DstPort 2
}
Line {
SrcBlock "tail_mux"
SrcPort 1
DstBlock "Rate Matching"
DstPort 1
}
Line {
SrcBlock "data source 01 ..10"
SrcPort 1
Points [0, 55]
Branch {
Points [0, 5]
DstBlock "Add CRC2"
DstPort 1
}
Branch {
Points [0, 275]
DstBlock "Delayed ber calculation"
DstPort 1
}
}
Line {
SrcBlock "inter_interleaving"
SrcPort 1
DstBlock "intra_interleaving"
DstPort 1
}
Line {
SrcBlock "control channel bits"
SrcPort 1
DstBlock "spreading1"
DstPort 1
}
Line {
SrcBlock "spreading1"
SrcPort 1
DstBlock "channel2"
DstPort 2
}
Line {
SrcBlock "spreading"
SrcPort 1
Points [60, 0]
DstBlock "channel2"
DstPort 1
}
Line {
SrcBlock "channel2"
SrcPort 2
DstBlock "Channel estimator"
DstPort 1
}
Line {
SrcBlock "channel2"
SrcPort 3
DstBlock "Channel estimator"
DstPort 2
}
Line {
SrcBlock "channel2"
SrcPort 1
DstBlock "ul_rake"
DstPort 1
}
Line {
SrcBlock "Channel estimator"
SrcPort 1
Points [0, 5]
DstBlock "ul_rake"
DstPort 2
}
Line {
SrcBlock "Channel estimator"
SrcPort 2
DstBlock "ul_rake"
DstPort 3
}
Line {
SrcBlock "Channel estimator"
SrcPort 3
Points [0, 5]
DstBlock "ul_rake"
DstPort 4
}
Line {
SrcBlock "channel2"
SrcPort 4
DstBlock "ul_rake"
DstPort 5
}
Line {
SrcBlock "Buffer"
SrcPort 2
Points [-20, 0]
DstBlock "intra_deinterleaving"
DstPort 2
}
Line {
SrcBlock "Buffer"
SrcPort 1
DstBlock "intra_deinterleaving"
DstPort 1
}
Line {
SrcBlock "intra_deinterleaving"
SrcPort 1
DstBlock "inter_deinterleaving"
DstPort 1
}
Line {
SrcBlock "intra_deinterleaving"
SrcPort 2
DstBlock "inter_deinterleaving"
DstPort 2
}
Line {
SrcBlock "ul_rake"
SrcPort 1
DstBlock "Buffer"
DstPort 1
}
Line {
SrcBlock "ul_rake"
SrcPort 2
Points [0, 40]
DstBlock "Buffer"
DstPort 2
}
Line {
SrcBlock "inter_deinterleaving"
SrcPort 1
DstBlock "rate_dematching"
DstPort 1
}
Line {
SrcBlock "ch_decoding"
SrcPort 1
DstBlock "remove CRC"
DstPort 1
}
Line {
SrcBlock "ch_decoding"
SrcPort 2
DstBlock "remove CRC"
DstPort 2
}
Line {
SrcBlock "rate_dematching"
SrcPort 1
DstBlock "ch_decoding"
DstPort 1
}
Line {
SrcBlock "rate_dematching"
SrcPort 2
DstBlock "ch_decoding"
DstPort 2
}
Line {
SrcBlock "inter_deinterleaving"
SrcPort 2
DstBlock "rate_dematching"
DstPort 2
}
Line {
SrcBlock "remove CRC"
SrcPort 2
DstBlock "To Workspace24"
DstPort 1
}
Line {
SrcBlock "remove CRC"
SrcPort 1
Points [-20, 0; 0, -350]
DstBlock "Delayed ber calculation"
DstPort 2
}
Line {
SrcBlock "Delayed ber calculation"
SrcPort 1
Points [45, 0]
Branch {
DstBlock "To Workspace23"
DstPort 1
}
Branch {
DstBlock "Display1"
DstPort 1
}
}
Annotation {
Position [195, 47]
Text "N = input block size"
}
Annotation {
Position [507, 787]
Text "\n\n\n"
}
}
}
}
}