www.pudn.com > UART.zip > uart_test_sdc.sdc, change:2007-08-19,size:310b


# Top Level Design Parameters 
 
# Clocks 
 
 
# False Paths Between Clocks 
 
 
# False Path Constraints 
 
 
# Maximum Delay Constraints 
 
 
# Multicycle Constraints 
 
 
# Virtual Clocks 
# Output Load Constraints 
# Driving Cell Constraints 
# Wire Loads 
# set_wire_load_mode top 
 
# Other Constraints