www.pudn.com > UART.zip > uart_test.tlg, change:2007-08-19,size:2464b


Selecting top level module uart_test 
@N: CG364 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":5:7:5:9|Synthesizing module rec 
 
@W: CG293 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":17:0:17:6|Ignoring initial statement 
@W: CG439 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":17:0:17:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":46:0:46:5|Pruning bit <9> of UartBuff_6[9:0] - not in use ... 
 
@N: CG364 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":6:7:6:10|Synthesizing module send 
 
@W: CG293 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":26:4:26:10|Ignoring initial statement 
@W: CG439 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":26:4:26:10|Initial statement will only initialize memories through the usage of $readmemh and $readmemb 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <9> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <8> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <7> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <6> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <5> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <4> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <3> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <2> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <1> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL189 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Register bit Datainbuf[0] is always 0, optimizing ... 
@W: CL189 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Register bit Datainbuf[9] is always 1, optimizing ... 
@W: CL171 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Pruning Register bit <9> of Datainbuf[9:0]  
 
@W: CL171 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Pruning Register bit <0> of Datainbuf[9:0]  
 
@N: CG364 :"C:\Actel_lab\Fusion_UART_lab\hdl\uart_test.v":5:7:5:15|Synthesizing module uart_test