www.pudn.com > UART.zip > uart_test.srr, change:2007-08-19,size:37796b


#Build: Synplify Pro 8.6.2H, Build 017R, Dec  7 2006 
#install: C:\Libero\Synplify\Synplify_862H 
#OS: Windows XP 5.1 
#Hostname: MAGUOFENG 
 
#Sun Aug 19 16:22:47 2007 
 
$ Start of Compile 
#Sun Aug 19 16:22:47 2007 
 
Synplicity Verilog Compiler, version 3.7, Build 090R, built Nov 17 2006 
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved 
 
@I::"C:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v" 
@I::"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v" 
@I::"C:\Actel_lab\Fusion_UART_lab\hdl\send.v" 
@I::"C:\Actel_lab\Fusion_UART_lab\hdl\uart_test.v" 
Verilog syntax check successful! 
 
Compiler output is up to date.  No re-compile necessary 
 
Selecting top level module uart_test 
@N: CG364 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":5:7:5:9|Synthesizing module rec 
 
@W: CG293 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":17:0:17:6|Ignoring initial statement 
@W: CG439 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":17:0:17:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\rec.v":46:0:46:5|Pruning bit <9> of UartBuff_6[9:0] - not in use ... 
 
@N: CG364 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":6:7:6:10|Synthesizing module send 
 
@W: CG293 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":26:4:26:10|Ignoring initial statement 
@W: CG439 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":26:4:26:10|Initial statement will only initialize memories through the usage of $readmemh and $readmemb 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <9> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <8> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <7> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <6> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <5> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <4> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <3> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <2> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL170 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":67:0:67:5|Pruning bit <1> of Datainbuf2_6[9:0] - not in use ... 
 
@W: CL189 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Register bit Datainbuf[0] is always 0, optimizing ... 
@W: CL189 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Register bit Datainbuf[9] is always 1, optimizing ... 
@W: CL171 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Pruning Register bit <9> of Datainbuf[9:0]  
 
@W: CL171 :"C:\Actel_lab\Fusion_UART_lab\hdl\send.v":55:0:55:5|Pruning Register bit <0> of Datainbuf[9:0]  
 
@N: CG364 :"C:\Actel_lab\Fusion_UART_lab\hdl\uart_test.v":5:7:5:15|Synthesizing module uart_test 
 
@END 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime 
# Sun Aug 19 16:22:47 2007 
 
###########################################################] 
Synplicity Proasic Technology Mapper, Version 9.0.0, Build 368R, Built Nov 27 2006 12:29:38 
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved 
Product Version Version 8.6.2H 
@N: MF249 |Running in 32-bit mode. 
@N: MF258 |Gated clock conversion disabled  
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W: BN153 |View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W: BN154 |View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 
 
 
RTL optimization done. 
 
Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 43MB peak: 45MB) 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\uart_test.v":34:16:34:25|Found 8 bit incrementor, 'senddata_1[7:0]' 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":35:6:35:14|Found 16 bit incrementor, 'un3_cnt_1[15:0]' 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":63:11:63:21|Found 4 bit incrementor, 'un7_count_1[3:0]' 
@W: BN116 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":46:0:46:5|Removing sequential instance UartBuff[0] of view:PrimLib.dff(prim) because there are no references to its outputs  
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":48:6:48:14|Found 16 bit incrementor, 'un3_cnt_1[15:0]' 
 
Finished factoring (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB) 
 
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB) 
 
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB) 
 
Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB) 
 
Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB) 
 
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 44MB peak: 45MB) 
 
Finished preparing to map (Time elapsed 0h:00m:03s; Memory used current: 45MB peak: 46MB) 
 
High Fanout Net Report 
********************** 
 
Driver Instance / Pin Name     Fanout, notes 
-------------------------------------------- 
uartrec.clkout / Y             15            
============================================ 
 
Promoting Net clock_c on CLKBUF  clock_pad 
Replicating clkrec, fanout 15 segments 2 
Buffering clksend, fanout 16 segments 2 
 
Finished technology mapping (Time elapsed 0h:00m:03s; Memory used current: 44MB peak: 46MB) 
 
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 44MB peak: 46MB) 
 
Added 1 Buffers 
Added 1 Cells via replication 
 
Finished restoring hierarchy (Time elapsed 0h:00m:03s; Memory used current: 44MB peak: 46MB) 
Writing Analyst data base C:\Actel_lab\Fusion_UART_lab\synthesis\uart_test.srm 
@N: BN225 |Writing default property annotation file C:\Actel_lab\Fusion_UART_lab\synthesis\uart_test.map. 
Writing EDIF Netlist and constraint files 
Found clock uart_test|clock with period 10.00ns  
Found clock rec|RI_inferred_clock with period 10.00ns  
Found clock send|clkout_inferred_clock with period 10.00ns  
 
 
##### START OF TIMING REPORT #####[ 
# Timing Report written on Sun Aug 19 16:22:55 2007 
# 
 
 
Top view:               uart_test 
Library name:           fusion 
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.58, P = 1.15, tree_type = balanced_tree ) 
Requested Frequency:    100.0 MHz 
Wire load mode:         top 
Wire load model:        fusion 
Paths requested:        5 
Constraint File(s):     
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 
 
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock.. 
 
 
 
Performance Summary  
******************* 
 
 
Worst slack in design: -1.196 
 
                               Requested     Estimated     Requested     Estimated                Clock        Clock               
Starting Clock                 Frequency     Frequency     Period        Period        Slack      Type         Group               
---------------------------------------------------------------------------------------------------------------------------------- 
send|clkout_inferred_clock     100.0 MHz     707.6 MHz     10.000        1.413         8.587      inferred     Inferred_clkgroup_2 
uart_test|clock                100.0 MHz     89.3 MHz      10.000        11.195        -1.196     inferred     Inferred_clkgroup_1 
================================================================================================================================== 
 
 
 
 
 
Clock Relationships 
******************* 
 
Clocks                                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise  
----------------------------------------------------------------------------------------------------------------------------------------------- 
Starting                    Ending                      |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack 
----------------------------------------------------------------------------------------------------------------------------------------------- 
rec|RI_inferred_clock       uart_test|clock             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -     
uart_test|clock             rec|RI_inferred_clock       |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -     
uart_test|clock             uart_test|clock             |  10.000      -1.196  |  No paths    -      |  No paths    -      |  No paths    -     
send|clkout_inferred_clock  uart_test|clock             |  Diff grp    -       |  No paths    -      |  No paths    -      |  No paths    -     
send|clkout_inferred_clock  send|clkout_inferred_clock  |  10.000      8.587   |  No paths    -      |  No paths    -      |  No paths    -     
=============================================================================================================================================== 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. 
 
 
 
Interface Information  
********************* 
 
		No IO constraint found  
 
 
 
==================================== 
Detailed Report for Clock: send|clkout_inferred_clock 
==================================== 
 
 
 
Starting Points with Worst Slack 
******************************** 
 
             Starting                                                  Arrival           
Instance     Reference                      Type     Pin     Net       Time        Slack 
             Clock                                                                       
---------------------------------------------------------------------------------------- 
WR_R1        send|clkout_inferred_clock     DFN1     Q       WR_R1     0.476       8.587 
WR_R2        send|clkout_inferred_clock     DFN1     Q       WR_R2     0.476       8.587 
======================================================================================== 
 
 
Ending Points with Worst Slack 
****************************** 
 
             Starting                                                  Required           
Instance     Reference                      Type     Pin     Net       Time         Slack 
             Clock                                                                        
----------------------------------------------------------------------------------------- 
WR_R2        send|clkout_inferred_clock     DFN1     D       WR_R1     9.590        8.587 
WR_R3        send|clkout_inferred_clock     DFN1     D       WR_R2     9.590        8.587 
========================================================================================= 
 
 
 
Worst Path Information 
*********************** 
 
 
Path information for path number 1:  
    Requested Period:                        10.000 
    - Setup time:                            0.410 
    = Required time:                         9.590 
 
    - Propagation time:                      1.003 
    = Slack (non-critical) :                 8.587 
 
    Number of logic level(s):                0 
    Starting point:                          WR_R1 / Q 
    Ending point:                            WR_R2 / D 
    The start point is clocked by            send|clkout_inferred_clock [rising] on pin CLK 
    The end   point is clocked by            send|clkout_inferred_clock [rising] on pin CLK 
 
Instance / Net              Pin      Pin               Arrival     No. of     
Name               Type     Name     Dir     Delay     Time        Fan Out(s) 
----------------------------------------------------------------------------- 
WR_R1              DFN1     Q        Out     0.476     0.476       -          
WR_R1              Net      -        -       0.527     -           2          
WR_R2              DFN1     D        In      -         1.003       -          
============================================================================= 
Total path delay (propagation time + setup) of 1.413 is 0.886(62.7%) logic and 0.527(37.3%) route. 
 
 
 
 
==================================== 
Detailed Report for Clock: uart_test|clock 
==================================== 
 
 
 
Starting Points with Worst Slack 
******************************** 
 
                     Starting                                            Arrival            
Instance             Reference           Type       Pin     Net          Time        Slack  
                     Clock                                                                  
------------------------------------------------------------------------------------------- 
uartrec.count[0]     uart_test|clock     DFN1E0     Q       count[0]     0.476       -1.196 
uartrec.count[1]     uart_test|clock     DFN1E0     Q       count[1]     0.476       -0.600 
uartrec.count[2]     uart_test|clock     DFN1E0     Q       count[2]     0.476       0.008  
uartrec.count[3]     uart_test|clock     DFN1E0     Q       count[3]     0.476       0.684  
uartrec.cnt[4]       uart_test|clock     DFN1       Q       cnt[4]       0.476       0.850  
uartrec.cnt[12]      uart_test|clock     DFN1       Q       cnt[12]      0.476       0.854  
uartrec.cnt[6]       uart_test|clock     DFN1       Q       cnt[6]       0.476       0.861  
uartrec.cnt[9]       uart_test|clock     DFN1       Q       cnt[9]       0.476       0.959  
uartrec.cnt[5]       uart_test|clock     DFN1       Q       cnt[5]       0.476       1.048  
uartrec.cnt[7]       uart_test|clock     DFN1       Q       cnt[7]       0.476       1.154  
=========================================================================================== 
 
 
Ending Points with Worst Slack 
****************************** 
 
                         Starting                                                  Required            
Instance                 Reference           Type       Pin     Net                Time         Slack  
                         Clock                                                                         
------------------------------------------------------------------------------------------------------ 
uartrec.StartF           uart_test|clock     DFN1E0     D       StartF_9           9.590        -1.196 
uartrec.count_bit[2]     uart_test|clock     DFN1       D       count_bit_1[2]     9.690        -0.606 
uartrec.UartBuff[1]      uart_test|clock     DFN1E1     E       N_91_i             9.650        -0.450 
uartrec.UartBuff[2]      uart_test|clock     DFN1E1     E       N_93_i             9.650        -0.450 
uartrec.UartBuff[3]      uart_test|clock     DFN1E1     E       N_95_i             9.650        -0.450 
uartrec.UartBuff[4]      uart_test|clock     DFN1E1     E       N_97_i             9.650        -0.450 
uartrec.UartBuff[5]      uart_test|clock     DFN1E1     E       N_99_i             9.650        -0.450 
uartrec.UartBuff[6]      uart_test|clock     DFN1E1     E       N_101_i            9.650        -0.450 
uartrec.UartBuff[7]      uart_test|clock     DFN1E1     E       N_103_i            9.650        -0.450 
uartrec.UartBuff[8]      uart_test|clock     DFN1E1     E       N_105_i            9.650        -0.450 
====================================================================================================== 
 
 
 
Worst Path Information 
*********************** 
 
 
Path information for path number 1:  
    Requested Period:                        10.000 
    - Setup time:                            0.410 
    = Required time:                         9.590 
 
    - Propagation time:                      10.786 
    = Slack (critical) :                     -1.196 
 
    Number of logic level(s):                9 
    Starting point:                          uartrec.count[0] / Q 
    Ending point:                            uartrec.StartF / D 
    The start point is clocked by            uart_test|clock [rising] on pin CLK 
    The end   point is clocked by            uart_test|clock [rising] on pin CLK 
 
Instance / Net                            Pin      Pin               Arrival     No. of     
Name                           Type       Name     Dir     Delay     Time        Fan Out(s) 
------------------------------------------------------------------------------------------- 
uartrec.count[0]               DFN1E0     Q        Out     0.476     0.476       -          
count[0]                       Net        -        -       1.650     -           8          
uartrec.un7_count_1.I_5        XOR2       A        In      -         2.127       -          
uartrec.un7_count_1.I_5        XOR2       Y        Out     0.361     2.488       -          
I_5_0                          Net        -        -       0.944     -           4          
uartrec.G_4_0                  OR2A       B        In      -         3.432       -          
uartrec.G_4_0                  OR2A       Y        Out     0.474     3.906       -          
G_4_0                          Net        -        -       0.313     -           1          
uartrec.G_4_1                  OR2A       B        In      -         4.219       -          
uartrec.G_4_1                  OR2A       Y        Out     0.474     4.693       -          
G_4_1                          Net        -        -       0.313     -           1          
uartrec.G_4                    OR2        A        In      -         5.006       -          
uartrec.G_4                    OR2        Y        Out     0.376     5.382       -          
G_4                            Net        -        -       0.527     -           2          
uartrec.count_bit_5_0.G_1      NOR2A      B        In      -         5.909       -          
uartrec.count_bit_5_0.G_1      NOR2A      Y        Out     0.304     6.213       -          
DWACT_ADD_CI_0_TMP[0]          Net        -        -       0.736     -           3          
uartrec.count_bit_5_0.G_2      NOR2B      B        In      -         6.948       -          
uartrec.count_bit_5_0.G_2      NOR2B      Y        Out     0.460     7.408       -          
G_2                            Net        -        -       0.313     -           1          
uartrec.count_bit_5_0.I_18     XOR2       B        In      -         7.721       -          
uartrec.count_bit_5_0.I_18     XOR2       Y        Out     0.681     8.402       -          
count_bit_5[2]                 Net        -        -       0.527     -           2          
uartrec.G_2                    OA1        B        In      -         8.928       -          
uartrec.G_2                    OA1        Y        Out     0.662     9.591       -          
N_2                            Net        -        -       0.527     -           2          
uartrec.G_0                    AO1A       A        In      -         10.118      -          
uartrec.G_0                    AO1A       Y        Out     0.355     10.473      -          
StartF_9                       Net        -        -       0.313     -           1          
uartrec.StartF                 DFN1E0     D        In      -         10.786      -          
=========================================================================================== 
Total path delay (propagation time + setup) of 11.196 is 5.032(44.9%) logic and 6.163(55.1%) route. 
 
 
Path information for path number 2:  
    Requested Period:                        10.000 
    - Setup time:                            0.410 
    = Required time:                         9.590 
 
    - Propagation time:                      10.721 
    = Slack (non-critical) :                 -1.131 
 
    Number of logic level(s):                9 
    Starting point:                          uartrec.count[0] / Q 
    Ending point:                            uartrec.StartF / D 
    The start point is clocked by            uart_test|clock [rising] on pin CLK 
    The end   point is clocked by            uart_test|clock [rising] on pin CLK 
 
Instance / Net                            Pin      Pin               Arrival     No. of     
Name                           Type       Name     Dir     Delay     Time        Fan Out(s) 
------------------------------------------------------------------------------------------- 
uartrec.count[0]               DFN1E0     Q        Out     0.476     0.476       -          
count[0]                       Net        -        -       1.650     -           8          
uartrec.un7_count_1.G_2        NOR3C      C        In      -         2.127       -          
uartrec.un7_count_1.G_2        NOR3C      Y        Out     0.484     2.611       -          
G_2_0                          Net        -        -       0.313     -           1          
uartrec.un7_count_1.G_0        XOR2       A        In      -         2.924       -          
uartrec.un7_count_1.G_0        XOR2       Y        Out     0.361     3.285       -          
G_0                            Net        -        -       0.944     -           4          
uartrec.G_4_1                  OR2A       A        In      -         4.230       -          
uartrec.G_4_1                  OR2A       Y        Out     0.399     4.629       -          
G_4_1                          Net        -        -       0.313     -           1          
uartrec.G_4                    OR2        A        In      -         4.942       -          
uartrec.G_4                    OR2        Y        Out     0.376     5.318       -          
G_4                            Net        -        -       0.527     -           2          
uartrec.count_bit_5_0.G_1      NOR2A      B        In      -         5.845       -          
uartrec.count_bit_5_0.G_1      NOR2A      Y        Out     0.304     6.148       -          
DWACT_ADD_CI_0_TMP[0]          Net        -        -       0.736     -           3          
uartrec.count_bit_5_0.G_2      NOR2B      B        In      -         6.884       -          
uartrec.count_bit_5_0.G_2      NOR2B      Y        Out     0.460     7.343       -          
G_2                            Net        -        -       0.313     -           1          
uartrec.count_bit_5_0.I_18     XOR2       B        In      -         7.657       -          
uartrec.count_bit_5_0.I_18     XOR2       Y        Out     0.681     8.337       -          
count_bit_5[2]                 Net        -        -       0.527     -           2          
uartrec.G_2                    OA1        B        In      -         8.864       -          
uartrec.G_2                    OA1        Y        Out     0.662     9.527       -          
N_2                            Net        -        -       0.527     -           2          
uartrec.G_0                    AO1A       A        In      -         10.054      -          
uartrec.G_0                    AO1A       Y        Out     0.355     10.408      -          
StartF_9                       Net        -        -       0.313     -           1          
uartrec.StartF                 DFN1E0     D        In      -         10.721      -          
=========================================================================================== 
Total path delay (propagation time + setup) of 11.131 is 4.968(44.6%) logic and 6.163(55.4%) route. 
 
 
Path information for path number 3:  
    Requested Period:                        10.000 
    - Setup time:                            0.310 
    = Required time:                         9.690 
 
    - Propagation time:                      10.296 
    = Slack (non-critical) :                 -0.606 
 
    Number of logic level(s):                9 
    Starting point:                          uartrec.count[0] / Q 
    Ending point:                            uartrec.count_bit[2] / D 
    The start point is clocked by            uart_test|clock [rising] on pin CLK 
    The end   point is clocked by            uart_test|clock [rising] on pin CLK 
 
Instance / Net                            Pin      Pin               Arrival     No. of     
Name                           Type       Name     Dir     Delay     Time        Fan Out(s) 
------------------------------------------------------------------------------------------- 
uartrec.count[0]               DFN1E0     Q        Out     0.476     0.476       -          
count[0]                       Net        -        -       1.650     -           8          
uartrec.un7_count_1.I_5        XOR2       A        In      -         2.127       -          
uartrec.un7_count_1.I_5        XOR2       Y        Out     0.361     2.488       -          
I_5_0                          Net        -        -       0.944     -           4          
uartrec.G_4_0                  OR2A       B        In      -         3.432       -          
uartrec.G_4_0                  OR2A       Y        Out     0.474     3.906       -          
G_4_0                          Net        -        -       0.313     -           1          
uartrec.G_4_1                  OR2A       B        In      -         4.219       -          
uartrec.G_4_1                  OR2A       Y        Out     0.474     4.693       -          
G_4_1                          Net        -        -       0.313     -           1          
uartrec.G_4                    OR2        A        In      -         5.006       -          
uartrec.G_4                    OR2        Y        Out     0.376     5.382       -          
G_4                            Net        -        -       0.527     -           2          
uartrec.count_bit_5_0.G_1      NOR2A      B        In      -         5.909       -          
uartrec.count_bit_5_0.G_1      NOR2A      Y        Out     0.304     6.213       -          
DWACT_ADD_CI_0_TMP[0]          Net        -        -       0.736     -           3          
uartrec.count_bit_5_0.G_2      NOR2B      B        In      -         6.948       -          
uartrec.count_bit_5_0.G_2      NOR2B      Y        Out     0.460     7.408       -          
G_2                            Net        -        -       0.313     -           1          
uartrec.count_bit_5_0.I_18     XOR2       B        In      -         7.721       -          
uartrec.count_bit_5_0.I_18     XOR2       Y        Out     0.681     8.402       -          
count_bit_5[2]                 Net        -        -       0.527     -           2          
uartrec.count_bit_0[2]         MX2        A        In      -         8.928       -          
uartrec.count_bit_0[2]         MX2        Y        Out     0.429     9.358       -          
N_11                           Net        -        -       0.313     -           1          
uartrec.count_bit_1[2]         OA1A       C        In      -         9.671       -          
uartrec.count_bit_1[2]         OA1A       Y        Out     0.312     9.982       -          
count_bit_1[2]                 Net        -        -       0.313     -           1          
uartrec.count_bit[2]           DFN1       D        In      -         10.296      -          
=========================================================================================== 
Total path delay (propagation time + setup) of 10.606 is 4.656(43.9%) logic and 5.950(56.1%) route. 
 
 
Path information for path number 4:  
    Requested Period:                        10.000 
    - Setup time:                            0.410 
    = Required time:                         9.590 
 
    - Propagation time:                      10.190 
    = Slack (non-critical) :                 -0.600 
 
    Number of logic level(s):                9 
    Starting point:                          uartrec.count[1] / Q 
    Ending point:                            uartrec.StartF / D 
    The start point is clocked by            uart_test|clock [rising] on pin CLK 
    The end   point is clocked by            uart_test|clock [rising] on pin CLK 
 
Instance / Net                            Pin      Pin               Arrival     No. of     
Name                           Type       Name     Dir     Delay     Time        Fan Out(s) 
------------------------------------------------------------------------------------------- 
uartrec.count[1]               DFN1E0     Q        Out     0.476     0.476       -          
count[1]                       Net        -        -       0.736     -           3          
uartrec.un7_count_1.I_5        XOR2       B        In      -         1.212       -          
uartrec.un7_count_1.I_5        XOR2       Y        Out     0.681     1.893       -          
I_5_0                          Net        -        -       0.944     -           4          
uartrec.G_4_0                  OR2A       B        In      -         2.837       -          
uartrec.G_4_0                  OR2A       Y        Out     0.474     3.311       -          
G_4_0                          Net        -        -       0.313     -           1          
uartrec.G_4_1                  OR2A       B        In      -         3.624       -          
uartrec.G_4_1                  OR2A       Y        Out     0.474     4.098       -          
G_4_1                          Net        -        -       0.313     -           1          
uartrec.G_4                    OR2        A        In      -         4.411       -          
uartrec.G_4                    OR2        Y        Out     0.376     4.787       -          
G_4                            Net        -        -       0.527     -           2          
uartrec.count_bit_5_0.G_1      NOR2A      B        In      -         5.314       -          
uartrec.count_bit_5_0.G_1      NOR2A      Y        Out     0.304     5.617       -          
DWACT_ADD_CI_0_TMP[0]          Net        -        -       0.736     -           3          
uartrec.count_bit_5_0.G_2      NOR2B      B        In      -         6.353       -          
uartrec.count_bit_5_0.G_2      NOR2B      Y        Out     0.460     6.813       -          
G_2                            Net        -        -       0.313     -           1          
uartrec.count_bit_5_0.I_18     XOR2       B        In      -         7.126       -          
uartrec.count_bit_5_0.I_18     XOR2       Y        Out     0.681     7.806       -          
count_bit_5[2]                 Net        -        -       0.527     -           2          
uartrec.G_2                    OA1        B        In      -         8.333       -          
uartrec.G_2                    OA1        Y        Out     0.662     8.996       -          
N_2                            Net        -        -       0.527     -           2          
uartrec.G_0                    AO1A       A        In      -         9.523       -          
uartrec.G_0                    AO1A       Y        Out     0.355     9.877       -          
StartF_9                       Net        -        -       0.313     -           1          
uartrec.StartF                 DFN1E0     D        In      -         10.190      -          
=========================================================================================== 
Total path delay (propagation time + setup) of 10.600 is 5.352(50.5%) logic and 5.249(49.5%) route. 
 
 
Path information for path number 5:  
    Requested Period:                        10.000 
    - Setup time:                            0.310 
    = Required time:                         9.690 
 
    - Propagation time:                      10.231 
    = Slack (non-critical) :                 -0.541 
 
    Number of logic level(s):                9 
    Starting point:                          uartrec.count[0] / Q 
    Ending point:                            uartrec.count_bit[2] / D 
    The start point is clocked by            uart_test|clock [rising] on pin CLK 
    The end   point is clocked by            uart_test|clock [rising] on pin CLK 
 
Instance / Net                            Pin      Pin               Arrival     No. of     
Name                           Type       Name     Dir     Delay     Time        Fan Out(s) 
------------------------------------------------------------------------------------------- 
uartrec.count[0]               DFN1E0     Q        Out     0.476     0.476       -          
count[0]                       Net        -        -       1.650     -           8          
uartrec.un7_count_1.G_2        NOR3C      C        In      -         2.127       -          
uartrec.un7_count_1.G_2        NOR3C      Y        Out     0.484     2.611       -          
G_2_0                          Net        -        -       0.313     -           1          
uartrec.un7_count_1.G_0        XOR2       A        In      -         2.924       -          
uartrec.un7_count_1.G_0        XOR2       Y        Out     0.361     3.285       -          
G_0                            Net        -        -       0.944     -           4          
uartrec.G_4_1                  OR2A       A        In      -         4.230       -          
uartrec.G_4_1                  OR2A       Y        Out     0.399     4.629       -          
G_4_1                          Net        -        -       0.313     -           1          
uartrec.G_4                    OR2        A        In      -         4.942       -          
uartrec.G_4                    OR2        Y        Out     0.376     5.318       -          
G_4                            Net        -        -       0.527     -           2          
uartrec.count_bit_5_0.G_1      NOR2A      B        In      -         5.845       -          
uartrec.count_bit_5_0.G_1      NOR2A      Y        Out     0.304     6.148       -          
DWACT_ADD_CI_0_TMP[0]          Net        -        -       0.736     -           3          
uartrec.count_bit_5_0.G_2      NOR2B      B        In      -         6.884       -          
uartrec.count_bit_5_0.G_2      NOR2B      Y        Out     0.460     7.343       -          
G_2                            Net        -        -       0.313     -           1          
uartrec.count_bit_5_0.I_18     XOR2       B        In      -         7.657       -          
uartrec.count_bit_5_0.I_18     XOR2       Y        Out     0.681     8.337       -          
count_bit_5[2]                 Net        -        -       0.527     -           2          
uartrec.count_bit_0[2]         MX2        A        In      -         8.864       -          
uartrec.count_bit_0[2]         MX2        Y        Out     0.429     9.294       -          
N_11                           Net        -        -       0.313     -           1          
uartrec.count_bit_1[2]         OA1A       C        In      -         9.607       -          
uartrec.count_bit_1[2]         OA1A       Y        Out     0.312     9.918       -          
count_bit_1[2]                 Net        -        -       0.313     -           1          
uartrec.count_bit[2]           DFN1       D        In      -         10.231      -          
=========================================================================================== 
Total path delay (propagation time + setup) of 10.541 is 4.592(43.6%) logic and 5.950(56.4%) route. 
 
 
 
##### END OF TIMING REPORT #####] 
 
-------------------------------------------------------------------------------- 
Report for cell uart_test.verilog 
  Core Cell usage: 
              cell count     area count*area 
              DFN1    52      1.0       52.0 
              XOR2    45      1.0       45.0 
              AND3    40      1.0       40.0 
             NOR2B    22      1.0       22.0 
            DFN1E1    21      1.0       21.0 
             NOR2A    15      1.0       15.0 
             NOR3C    15      1.0       15.0 
              NOR2    10      1.0       10.0 
              OA1A     9      1.0        9.0 
             NOR3B     9      1.0        9.0 
              MX2C     7      1.0        7.0 
              AND2     7      1.0        7.0 
            DFN1E0     7      1.0        7.0 
               MX2     5      1.0        5.0 
              OR2B     4      1.0        4.0 
             NOR3A     4      1.0        4.0 
               INV     3      1.0        3.0 
               GND     3      0.0        0.0 
              OR2A     3      1.0        3.0 
               VCC     3      0.0        0.0 
              AO1A     2      1.0        2.0 
              OR3C     2      1.0        2.0 
              BUFF     1      1.0        1.0 
              OA1C     1      1.0        1.0 
             XNOR2     1      1.0        1.0 
               OR3     1      1.0        1.0 
               OA1     1      1.0        1.0 
              OA1B     1      1.0        1.0 
               OR2     1      1.0        1.0 
              AX1C     1      1.0        1.0 
               AX1     1      1.0        1.0 
               AO1     1      1.0        1.0 
             AOI1B     1      1.0        1.0 
              NOR3     1      1.0        1.0 
              MAJ3     1      1.0        1.0 
              OAI1     1      1.0        1.0 
                   -----          ---------- 
             TOTAL   302               296.0 
 
 
  IO Cell usage: 
              cell count 
             INBUF     1 
            CLKBUF     1 
            OUTBUF     1 
                   ----- 
             TOTAL     3 
Mapper successful! 
Process took 0h:00m:04s realtime, 0h:00m:03s cputime 
# Sun Aug 19 16:22:55 2007 
 
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