www.pudn.com > UART.zip > uart_test.msg, change:2007-08-19,size:1955b


@TM:1185781108 
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK0": remove clock marking 
@W: BN153 :"":0:0:0:-1|View "prim", Cell "NGMUX", Port "CLK1": remove clock marking 
@W: BN154 :"":0:0:0:-1|View "prim" of Cell "NGMUX": 4 sequential timing arcs are removed 
@TM:1187510654 
@N: BN225 :"":0:0:0:-1|Writing default property annotation file C:\Actel_lab\Fusion_UART_lab\synthesis\uart_test.map. 
@TM:1185781108 
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode. 
@TM:1185852158 
@N: MF258 :"":0:0:0:-1|Gated clock conversion disabled  
@TM:1185781108 
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock.. 
@TM:1187510654 
@N: CG364 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":5:7:5:9|Synthesizing module rec 
@W: CG293 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":17:0:17:6|M 
@W: CG439 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":17:0:17:6|M 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":35:6:35:14|M 
@W: BN116 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":46:0:46:5|M 
@W: CL170 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":46:0:46:5|M 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\rec.v":63:11:63:21|M 
@N: CG364 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":6:7:6:10|Synthesizing module send 
@W: CG293 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":26:4:26:10|M 
@W: CG439 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":26:4:26:10|M 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":48:6:48:14|M 
@W: CL171 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":55:0:55:5|M 
@W: CL189 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":55:0:55:5|M 
@W: CL170 :"c:\actel_lab\fusion_uart_lab\hdl\send.v":67:0:67:5|M 
@N: CG364 :"c:\actel_lab\fusion_uart_lab\hdl\uart_test.v":5:7:5:15|Synthesizing module uart_test 
@N: MF238 :"c:\actel_lab\fusion_uart_lab\hdl\uart_test.v":34:16:34:25|M