www.pudn.com > UART.zip > run_options.txt, change:2007-07-30,size:1310b


#-- Synplicity, Inc. 
#-- Version Synplify 8.8A1 
#-- Project file E:\uart\synthesis\run_options.txt 
#-- Written on Mon Jul 30 15:38:21 2007 
 
 
#add_file options 
add_file -verilog "E:/uart/hdl/send.v" 
add_file -verilog "E:/uart/hdl/rec.v" 
add_file -verilog "E:/uart/hdl/uart_test.v" 
 
 
#implementation: "synthesis" 
impl -add synthesis -type fpga 
 
#device options 
set_option -technology Fusion 
set_option -part AFS600 
set_option -package "" 
set_option -speed_grade -2 
set_option -part_companion "" 
 
#compilation/mapping options 
set_option -default_enum_encoding default 
set_option -resource_sharing 1 
 
#map options 
set_option -frequency 100.000 
set_option -run_prop_extract 1 
set_option -fanout_limit 12 
set_option -globalthreshold 50 
set_option -maxfan_hard 0 
set_option -disable_io_insertion 0 
set_option -retiming 0 
set_option -report_path 4000 
set_option -update_models_cp 0 
set_option -preserve_registers 0 
 
 
#sequential_optimizations options 
set_option -symbolic_fsm_compiler 1 
 
#simulation options 
set_option -write_verilog 0 
set_option -write_vhdl 0 
 
#automatic place and route (vendor) options 
set_option -write_apr_constraint 1 
 
#set result format/file last 
project -result_format "edif" 
project -result_file "./uart_test.edn" 
impl -active "synthesis"