www.pudn.com > UART.zip > uart_test_tbench.v, change:2007-07-31,size:6616b


// Generated by WaveFormer Lite Version 11.14a at 16:40:59 on 7/31/2007 
// Stimulator for stimulus 
 
// Generation Settings: 
//   Export type: Stimulus only (reactive export not enabled) 
//                Delays, Samples, Markers, etc will not generate code. 
 
// Clock Domains: 
 
//   Unclocked 
//   --------- 
//     Signals: 
//       RXD 
//     Markers: 
//       MARK0 (End Diagram) 
 
 
`define TB_ABORT (3'b000) 
`define TB_ONCE (3'b001) 
`define TB_DONE (3'b010) 
`define TB_LOOPING (3'b011) 
`define TB_RESTART (3'b100) 
`define TB_END (3'b101) 
`timescale  1 ns /  1 ps 
 
module stimulus(clock, RXD); 
  output clock; 
  output RXD; 
  reg RXD_driver; 
  assign RXD = RXD_driver; 
 
 
  // Control Signal Declarations 
  reg [2:0] tb_status; 
 
  // Parm Declarations 
  real clock_MinHL; 
  real clock_MaxHL; 
  real clock_MinLH; 
  real clock_MaxLH; 
  real clock_JFall; 
  real clock_JRise; 
  real clock_Duty; 
  real clock_Period; 
  real clock_Offset; 
 
 
  // The following initial block will start up the stimulator. 
  initial 
    begin 
    AssignParms; 
    tb_status <= `TB_ONCE; 
    Unclocked; 
    tb_status <= `TB_DONE; 
    $display("Note: At %t: End of stimulus reached.  Use End Diagram Marker to extend or shorten stimulus.", $time); 
    end 
 
  // Parm Assignment Task 
  task AssignParms; 
    begin 
    clock_MinHL = 0.0; 
    clock_MaxHL = 0.0; 
    clock_MinLH = 0.0; 
    clock_MaxLH = 0.0; 
    clock_JFall = 0.0; 
    clock_JRise = 0.0; 
    clock_Duty = 50.0; 
    clock_Period = 100.0; 
    clock_Offset = 0.0; 
    end 
  endtask 
 
  // Clocks 
 
  // Clock Instantiation 
  wire [63:0] clock_Offset_bits = $realtobits(clock_Offset); 
  wire [63:0] clock_Period_bits = $realtobits(clock_Period); 
  wire [63:0] clock_Duty_bits = $realtobits(clock_Duty); 
  wire [63:0] clock_JRise_bits = $realtobits(clock_JRise); 
  wire [63:0] clock_JFall_bits = $realtobits(clock_JFall); 
  wire [63:0] clock_MinLH_bits = $realtobits(clock_MinLH); 
  wire [63:0] clock_MaxLH_bits = $realtobits(clock_MaxLH); 
  wire [63:0] clock_MinHL_bits = $realtobits(clock_MinHL); 
  wire [63:0] clock_MaxHL_bits = $realtobits(clock_MaxHL); 
  tb_clock_minmax #(1) tb_clock(tb_status[1:0], 
            clock, 
            clock_Offset_bits, 
            clock_Period_bits, 
            clock_Duty_bits, 
            clock_MinLH_bits, 
            clock_MaxLH_bits, 
            clock_MinHL_bits, 
            clock_MaxHL_bits, 
            clock_JRise_bits, 
            clock_JFall_bits); 
 
  // Clocked Sequences 
 
  // Sequence: Unclocked 
 
  // Drive signals to their initial values 
  initial 
    begin 
    RXD_driver <= 1'b0; 
    end 
 
  task Unclocked; 
    begin 
    #982086; 
    RXD_driver <= 1'b1; 
    #1312847; 
    RXD_driver <= 1'b0; 
    #858399; 
    RXD_driver <= 1'b1; 
    #656424; 
    RXD_driver <= 1'b0; 
    #1077207; 
    RXD_driver <= 1'b1; 
    #1077207; 
    RXD_driver <= 1'b0; 
    #1296015; 
    RXD_driver <= 1'b1; 
    #1195027; 
    RXD_driver <= 1'b0; 
    #942557; 
    RXD_driver <= 1'b1; 
    #2423716; 
    RXD_driver <= 1'b0; 
    #2272234; 
    RXD_driver <= 1'b1; 
    #7757782; 
    RXD_driver <= 1'b0; 
    #6093207; 
    RXD_driver <= 1'b1; 
    #71836292; 
    // End Diagram Marker: MARK0 
    $finish; 
    end 
  endtask 
endmodule 
 
// Clock models used by diagram. 
 
// Copied contents of file: d:\Libero\WFL\lib\verilog\tb_clock_minmax.v 
 
module tb_clock_minmax(tb_status, CLK, offset_bits, period_bits, duty_bits, minLH_bits, maxLH_bits, minHL_bits, maxHL_bits, jRise_bits, jFall_bits); 
  parameter initialize = 0; 
 
  input [1:0] tb_status; 
  output CLK; 
  input [63:0] offset_bits; 
  input [63:0] period_bits; 
  input [63:0] duty_bits; 
  input [63:0] minLH_bits; 
  input [63:0] maxLH_bits; 
  input [63:0] minHL_bits; 
  input [63:0] maxHL_bits; 
  input [63:0] jRise_bits; 
  input [63:0] jFall_bits; 
 
  reg  CLK; 
  real offset; 
  real period; 
  real duty; 
  real minLH; 
  real maxLH; 
  real minHL; 
  real maxHL; 
  real jRise; 
  real jFall; 
  real CLK_high; 
  real CLK_low; 
  
  task DriveLHInvalidRegion; 
    begin 
    if ( (jRise + maxLH - minLH) > 0.0 ) 
      begin 
      CLK <= 1'bx; 
      #((jRise + maxLH - minLH)); 
      end 
    end 
  endtask 
 
  task DriveHLInvalidRegion; 
    begin 
    if ( (jFall + maxHL - minHL) > 0.0 ) 
      begin 
      CLK <= 1'bx; 
      #((jFall + maxHL - minHL)); 
      end 
    end 
  endtask 
 
  always 
    begin 
    @(posedge tb_status[0]) 
    offset = $bitstoreal( offset_bits ); 
    period = $bitstoreal( period_bits ); 
    duty  = $bitstoreal( duty_bits ); 
    minLH = $bitstoreal( minLH_bits ); 
    maxLH = $bitstoreal( maxLH_bits ); 
    minHL = $bitstoreal( minHL_bits ); 
    maxHL = $bitstoreal( maxHL_bits ); 
    jRise = $bitstoreal( jRise_bits ); 
    jFall = $bitstoreal( jFall_bits ); 
    if (period <= 0.0) 
      $display("Error: Period for clock %m is invalid (period=%f).  Clock will not be driven", period); 
    else if (duty <= 0.0) 
      $display("Error: Duty for clock %m is invalid (duty=%f).  Clock will not be driven", duty); 
    else 
      begin 
      CLK_high = period * duty / 100; 
      CLK_low = period - CLK_high; 
       
      if ( (offset + (minLH - jRise/2)) >= 0.0 ) 
        begin 
        if (initialize) 
          CLK <= 1'b0; // drive initial state 
        #(offset + (minLH - jRise/2)) 
        ; 
        end 
      else 
        begin // wait for x 
        if (initialize) 
          CLK <= 1'bx; // in middle of X region, init to X 
        #((jRise/2 + maxLH) + (offset)) 
        CLK <= 1'b1; 
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2))) 
        DriveHLInvalidRegion; 
        CLK <= 1'b0; 
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2))) 
        ; 
        end 
   
      while ( tb_status[0] == 1'b1 ) 
        begin : clock_loop 
        DriveLHInvalidRegion; 
        CLK <= 1'b1; 
        #((CLK_high - (maxLH + jRise/2) + (minHL - jFall/2))) 
        DriveHLInvalidRegion; 
        CLK <= 1'b0; 
        #((CLK_low - (maxHL + jFall/2) + (minLH - jRise/2))) 
        ; 
        end 
      end 
    end 
endmodule 
 
// End of contents of file: d:\Libero\WFL\lib\verilog\tb_clock_minmax.v 
 
// Test Bench wrapper for stimulus and Model Under Test 
 
module testbench; 
  wire clock; 
  wire RXD; 
  wire TXD; 
 
  // Stimulator instance 
  stimulus stimulus_0(.clock(clock), 
            .RXD(RXD)); 
 
  // Instantiation of Model Under Test. 
  uart_test uart_test_0(.clock(clock), 
            .RXD(RXD), 
            .TXD(TXD)); 
endmodule