www.pudn.com > UART.zip > uart_test.hpj, change:2007-07-31,size:890b


<!DOCTYPE SimulationProject SYSTEM "hdl-prj.dtd"> 
<SimulationProject ProductVersion="8.6c" Logfile="uart_test.log" AutoParseProject="1" NameOfComponentToParse="uart_test" Keyfile="verilog.key" Language="Verilog" DelayType="typical" AddTopLevelSignals="0" FileNamesShown="1" HideEmptyLists="1" ShowWatch="1" DumpWatch="0" InteractiveMode="1" ParametersAreWatchable="0" ClearLogBeforeCompile="1" CreateLogFileDuringSim="1" >  
  <FileList> 
    <File>E:\uart\hdl\uart_test.v</File> 
  </FileList> 
  <DirList> 
    <Directory>d:\Libero\WFL\</Directory> 
    <Directory>E:\uart\hdl</Directory> 
  </DirList> 
  <LibDirList> 
    <Directory>d:\Libero\WFL\lib\verilog\</Directory> 
    <Directory>D:\Libero\Designer/lib/vlog/fusion.v</Directory> 
  </LibDirList> 
  <LibExtensionList> 
    <Extension>.v</Extension> 
    <Extension>.vo</Extension> 
  </LibExtensionList> 
</SimulationProject>