www.pudn.com > 1553B_enc_dec.rar > decoder_1553.vif, change:2011-12-04,size:1342b


# 
# Synplicity Verification Interface File 
# Generated using Synplify-pro 
# 
# Copyright (c) 1996-2008 Synplicity, Inc. 
# All rights reserved 
# 
 
# Set logfile options 
vif_set_result_file  decoder_1553.vlf 
 
# Set technology for TCL script 
vif_set_technology -architecture FPGA -vendor Xilinx 
 
# RTL and technology files 
vif_add_library -original $XILINX/verilog/verification/unisims 
vif_add_library -original $XILINX/verilog/verification/simprims 
vif_add_file -original -verilog ../../../../source/decoder_1553.v 
vif_set_top_module -original -top decoder_1553 
  
vif_add_library -translated $XILINX/verilog/verification/unisims 
vif_add_library -translated $XILINX/verilog/verification/simprims 
vif_add_file -translated -verilog decoder_1553.vm 
vif_set_top_module -translated -top decoder_1553  
# Read FSM encoding 
 
# Memory map points 
 
# SRL map points 
 
# Compiler constant registers 
 
# Compiler constant latches 
 
# Compiler RTL sequential redundancies 
 
# RTL sequential redundancies 
 
# Technology sequential redundancies 
 
# Inversion map points 
 
# Port mappping and directions 
 
# Black box mapping 
 
 
# Other sequential cells, including multidimensional arrays 
vif_set_map_point -register -original sync_sftreg[23] -translated sync_sftreg_0_Z[23] 
 
# Constant Registers 
 
# Retimed Registers