www.pudn.com > 1553B_enc_dec.rar > run_options.txt, change:2011-12-04,size:1577b


#-- Synopsys, Inc. 
#-- Version 9.6.2 
#-- Project file F:\prj\1553b\1553_enc_dec\synthesis\EC\synplify\rev_1\run_options.txt 
#-- Written on Sun Dec 04 10:45:19 2011 
 
 
#add_file options 
add_file -verilog "F:/prj/1553b/1553_enc_dec/source/decoder_1553.v" 
add_file -constraint "./decoder_1553.sdc" 
 
 
#implementation: "rev_1" 
impl -add rev_1 -type fpga 
 
#device options 
set_option -technology SPARTAN3A 
set_option -part XC3S50A 
set_option -package TQ144 
set_option -speed_grade -4 
set_option -part_companion "" 
 
#compilation/mapping options 
set_option -default_enum_encoding default 
set_option -resource_sharing 1 
set_option -use_fsm_explorer 0 
set_option -top_module "decoder_1553" 
 
#map options 
set_option -frequency 8.000 
set_option -vendor_xcompatible_mode 0 
set_option -vendor_xcompatible_mode 0 
set_option -run_prop_extract 1 
set_option -fanout_limit 10000 
set_option -disable_io_insertion 0 
set_option -pipe 1 
set_option -retiming 0 
set_option -update_models_cp 0 
set_option -fixgatedclocks 3 
set_option -fixgeneratedclocks 3 
set_option -verification_mode 0 
set_option -no_sequential_opt 0 
 
 
#sequential_optimizations options 
set_option -symbolic_fsm_compiler 1 
 
#simulation options 
set_option -write_verilog 0 
set_option -write_vhdl 0 
 
#VIF options 
set_option -write_vif 1 
 
#automatic place and route (vendor) options 
set_option -write_apr_constraint 1 
 
#set result format/file last 
project -result_file "./rev_1/decoder_1553.edf" 
 
# 
#implementation attributes 
 
set_option -vlog_std v2001 
impl -active "rev_1"