www.pudn.com > 1553B_enc_dec.rar > encoder_1553_synplify.lpf, change:2011-09-14,size:1475b


# 
# Logical Preferences generated for Lattice by Synplify 9.6, Build 030R. 
# 
 
# Period Constraints 
FREQUENCY PORT "enc_clk" 2.0 MHz; 
# Output Constraints 
CLOCK_TO_OUT "tx_busy" 450 NS CLKPORT = "enc_clk"; 
CLOCK_TO_OUT "tx_data" 450 NS CLKPORT = "enc_clk"; 
CLOCK_TO_OUT "tx_dval" 450 NS CLKPORT = "enc_clk"; 
# Input Constraints 
INPUT_SETUP "tx_dword_15" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_14" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_13" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_12" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_11" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_10" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_9" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_8" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_7" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_6" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_5" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_4" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_3" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_2" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_1" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dword_0" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_csw" 450 NS CLKPORT = "enc_clk"; 
INPUT_SETUP "tx_dw" 450 NS CLKPORT = "enc_clk"; 
 
#Begin false path from constraints 
BLOCK PATH FROM PORT "rst_n";  
#End false path from constraints 
 
BLOCK ASYNCPATHS; 
 
# End of generated Logical Preferences.