www.pudn.com > 1553B_enc_dec.rar > decoder_1553.srr, change:2011-09-14,size:17345b
#Build: Synplify Pro 9.6.2, Build 066R, Oct 28 2008
#install: D:\Softwares\Synplify\fpga_962
#OS: 6.1
#Hostname: WANGLONG
#Implementation: rev_1
#Wed Sep 14 13:54:56 2011
$ Start of Compile
#Wed Sep 14 13:54:56 2011
Synplicity Verilog Compiler, version 1.0, Build 037R, built Oct 30 2008
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
@I::"D:\Softwares\Synplify\fpga_962\lib\xilinx\unisim.v"
@I::"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v"
Verilog syntax check successful!
Selecting top level module decoder_1553
@N: CG364 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":45:7:45:18|Synthesizing module decoder_1553
@N: CG179 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":127:17:127:23|Removing redundant assignment
@N: CG179 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":138:13:138:15|Removing redundant assignment
@N: CG179 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":154:19:154:27|Removing redundant assignment
@N: CG179 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":167:22:167:33|Removing redundant assignment
@N: CG179 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":179:21:179:31|Removing redundant assignment
@W: CG360 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":87:15:87:23|No assignment to wire sync_edge
@W: CG360 :"F:\prj\1553b\1553_enc_dec\source\decoder_1553.v":92:15:92:20|No assignment to wire parity
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Sep 14 13:54:57 2011
###########################################################]
Synplicity Xilinx Technology Mapper, Version 9.6, Build 033R, Built Oct 30 2008 18:01:10
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
Product Version Version 9.6.2
Reading constraint file: F:\prj\1553b\1553_enc_dec\synthesis\EC\synplify\decoder_1553.sdc
Adding property syn_input_delay1, value "r=50.00,f=50.00,rs=0.0,fs=0.0,improve=0.00,route=0.00,ref=dec_clk:r" to view:work.decoder_1553(verilog)
Adding property syn_output_delay2, value "r=50.00,f=50.00,rs=0.0,fs=0.0,improve=0.00,route=0.00,ref=dec_clk:r" to view:work.decoder_1553(verilog)
Adding property syn_false_path1011, value "from p:rst_n" to view:work.decoder_1553(verilog)
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled
Reading Xilinx I/O pad type table from file <D:\Softwares\Synplify\fpga_962\lib\xilinx\x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <D:\Softwares\Synplify\fpga_962\lib\xilinx\gttype.txt>
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
@N:"f:\prj\1553b\1553_enc_dec\source\decoder_1553.v":130:0:130:5|Found counter in view:work.decoder_1553(verilog) inst cnt[7:0]
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[
================================================================
Instance:Pin Generated Clock Optimization Status
================================================================
######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Clock Buffers:
Inserting Clock buffer for port dec_clk,
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 95MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Net buffering Report for view:work.decoder_1553(verilog):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 94MB peak: 95MB)
@N: FX164 |The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 94MB peak: 95MB)
Writing Analyst data base F:\prj\1553b\1553_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.srm
@N: BN225 |Writing default property annotation file F:\prj\1553b\1553_enc_dec\synthesis\EC\synplify\rev_1\decoder_1553.map.
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 94MB peak: 95MB)
Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file <D:\Softwares\Synplify\fpga_962\lib\xilinx\netattr.txt>
Version 9.6.2
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 94MB peak: 95MB)
Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 95MB peak: 95MB)
@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 95MB peak: 95MB)
Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 95MB peak: 95MB)
@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 95MB peak: 95MB)
Found clock dec_clk with period 100.00ns
All Input Ports in the design have input constraint of 50.00ns w.r.t. clock dec_clk:r
All Output Ports in the design have output constraint of 50.00ns w.r.t. clock dec_clk:r
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Sep 14 13:55:01 2011
#
Top view: decoder_1553
Requested Frequency: 10.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s): F:\prj\1553b\1553_enc_dec\synthesis\EC\synplify\decoder_1553.sdc
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary
*******************
Worst slack in design: 45.631
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
---------------------------------------------------------------------------------------------------------------------
dec_clk 10.0 MHz 18.4 MHz 100.000 54.369 45.631 declared default_clkgroup_0
=====================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
----------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
----------------------------------------------------------------------------------------------------------
dec_clk dec_clk | 100.000 45.631 | No paths - | No paths - | No paths -
==========================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-------------------------------------------------------------------------------
dec_clk NA NA NA NA NA
rst_n dec_clk (rising) 50.000 NA NA NA
rx_data dec_clk (rising) 50.000 50.000 96.960 46.960
===============================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
------------------------------------------------------------------------------------------------
rx_csw dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dval dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dw dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[0] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[1] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[2] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[3] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[4] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[5] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[6] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[7] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[8] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[9] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[10] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[11] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[12] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[13] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[14] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_dword[15] dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
rx_perr dec_clk (rising) 50.000(dec_clk rising) 4.369 50.000 45.631
================================================================================================
====================================
Detailed Report for Clock: dec_clk
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-----------------------------------------------------------------------------------
rx_csw dec_clk FDC Q rx_csw_c 0.000 45.631
rx_dval dec_clk FDC Q rx_dval_c 0.000 45.631
rx_dw dec_clk FDC Q rx_dw_c 0.000 45.631
rx_dword[0] dec_clk FDC Q rx_dword_c[0] 0.000 45.631
rx_dword[1] dec_clk FDC Q rx_dword_c[1] 0.000 45.631
rx_dword[2] dec_clk FDC Q rx_dword_c[2] 0.000 45.631
rx_dword[3] dec_clk FDC Q rx_dword_c[3] 0.000 45.631
rx_dword[4] dec_clk FDC Q rx_dword_c[4] 0.000 45.631
rx_dword[5] dec_clk FDC Q rx_dword_c[5] 0.000 45.631
rx_dword[6] dec_clk FDC Q rx_dword_c[6] 0.000 45.631
===================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
---------------------------------------------------------------------------------------------
rx_csw dec_clk Port rx_csw rx_csw 50.000 45.631
rx_dval dec_clk Port rx_dval rx_dval 50.000 45.631
rx_dw dec_clk Port rx_dw rx_dw 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[0] rx_dword[0] 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[1] rx_dword[1] 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[2] rx_dword[2] 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[3] rx_dword[3] 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[4] rx_dword[4] 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[5] rx_dword[5] 50.000 45.631
rx_dword[0:15] dec_clk Port rx_dword[6] rx_dword[6] 50.000 45.631
=============================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 100.000
- User constraint on ending point: 50.000
+ Clock delay at ending point: 0.000 (ideal)
= Required time: 50.000
- Propagation time: 4.369
- Clock delay at starting point: 0.000 (ideal)
= Slack (critical) : 45.631
Number of logic level(s): 1
Starting point: rx_csw / Q
Ending point: rx_csw / rx_csw
The start point is clocked by dec_clk [rising] on pin C
The end point is clocked by dec_clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------
rx_csw FDC Q Out 0.000 0.000 -
rx_csw_c Net - - 0.000 - 1
rx_csw_obuf OBUF I In - 0.000 -
rx_csw_obuf OBUF O Out 4.369 4.369 -
rx_csw Net - - 0.000 - 1
rx_csw Port rx_csw Out - 4.369 -
===============================================================================
Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 4.369 is 4.369(100.0%) logic and 0.000(0.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
*Arrival time includes intrinsic clock delay at start point and clock delay at startpoint
##### END OF TIMING REPORT #####]
@W: MT305 |Timing constraint (from p:rst_n) (false path) never applies in design and was not found in design. To be verified
---------------------------------------
Resource Usage Report for decoder_1553
Mapping to part: xc3s50atq144-4
Cell usage:
FDC 49 uses
FDCE 20 uses
FDP 8 uses
GND 1 use
MUXCY 2 uses
MUXCY_L 19 uses
VCC 1 use
XORCY 8 uses
LUT1 2 uses
LUT2 30 uses
LUT3 20 uses
LUT4 22 uses
I/O ports: 23
I/O primitives: 22
IBUF 2 uses
OBUF 20 uses
BUFGP 1 use
I/O Register bits: 21
Register bits not including I/Os: 56 (3%)
Global Clock Buffers: 1 of 24 (4%)
Total load per clock:
dec_clk: 77
Mapping Summary:
Total LUTs: 74 (5%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Sep 14 13:55:01 2011
###########################################################]