www.pudn.com > DDS.zip > DDS.V, change:2011-07-19,size:1218b


`timescale 1ns / 1ps 
////////////////////////////////////////////////////////////////////////////////// 
// Company:  
// Engineer: Jianneng Chen 
//  
// Create Date:    19:16:57 07/17/2011  
// Design Name: dds 
// Module Name:    ram & led  
// Project Name: dds1 
// Target Devices: xc3s100e-5cp132 
// Tool versions:  
// Description:  
// 
// Dependencies:  
// 
// Revision:  
// Revision 0.01 - File Created 
// Additional Comments:  
// 
////////////////////////////////////////////////////////////////////////////////// 
module DDS1(ledout, clk, r, key1); 
input clk; 
input[7:0] key1; 
output[3:0] r; 
output[7:0] ledout; 
 
reg[7:0] t; 
reg[25:0] n; 
wire[7:0] led; 
reg[7:0] temp; 
reg flag, a; 
 
initial  
begin 
	n = 0; 
	t = 0; 
	flag = 1; 
	a = 0; 
end 
 
assign r = 0; 
 
always @(posedge clk) 
begin 
	n = n + 1; 
	if(flag == 1 && n == key1*64) 
	begin 
		n = 0; 
		t = t + 1; 
		if(t == 255) 
		begin 
			flag = 0; 
		end 
	end 
	else if(flag == 0 &&  n == key1*64) 
	begin 
		 n = 0; 
		 t = t - 1; 
		 if(t == 0) 
		 begin 
			flag = 1; 
			a = ~a; 
		 end 
	end	 
	if(a == 1) 
		temp = led; 
	else  
		temp = 8'h99-led; 
end 
 
dds ua(.a(t), .spo(led)); 
 
assign ledout = temp; 
 
endmodule