www.pudn.com > 16QAM_verilog.rar > _primary.vhd, change:2011-07-14,size:321b


library verilog;
use verilog.vl_types.all;
entity qam16 is
    port(
        clk             : in     vl_logic;
        clk12p5MHz      : in     vl_logic;
        reset           : in     vl_logic;
        x               : in     vl_logic;
        y               : out    vl_logic_vector(17 downto 0)
    );
end qam16;