www.pudn.com > 16QAM_verilog.rar > _primary.vhd, change:2011-07-14,size:468b


library verilog;
use verilog.vl_types.all;
entity ddsqam is
    port(
        DATA            : in     vl_logic_vector(24 downto 0);
        WE              : in     vl_logic;
        A               : in     vl_logic_vector(4 downto 0);
        CLK             : in     vl_logic;
        CE              : in     vl_logic;
        SINE            : out    vl_logic_vector(15 downto 0);
        COSINE          : out    vl_logic_vector(15 downto 0)
    );
end ddsqam;