www.pudn.com > 16QAM_verilog.rar > coregen.xml, change:2011-07-13,size:1641b


<?xml version="1.0" encoding="UTF-8"?> 
<RootFolder label="COREGEN" treetype="folder" language="COREGEN"> 
	<Folder label="VERILOG Component Instantiation" treetype="folder"> 
		<Template label="ddsqam" treetype="template"> 
  
  
// The following must be inserted into your Verilog file for this 
// core to be instantiated. Change the instance name and port connections 
// (in parentheses) to your own signal names. 
  
ddsqam YourInstanceName ( 
    .DATA(DATA), // Bus [24 : 0]  
    .WE(WE), 
    .A(A), // Bus [4 : 0]  
    .CLK(CLK), 
    .CE(CE), 
    .SINE(SINE), // Bus [15 : 0]  
    .COSINE(COSINE)); // Bus [15 : 0]  
 
  
		</Template> 
	</Folder> 
	<Folder label="VHDL Component Instantiation" treetype="folder"> 
		<Template label="ddsqam" treetype="template"> 
  
  
-- The following code must appear in the VHDL architecture header: 
  
component ddsqam 
    port ( 
    DATA: IN std_logic_VECTOR(24 downto 0); 
    WE: IN std_logic; 
    A: IN std_logic_VECTOR(4 downto 0); 
    CLK: IN std_logic; 
    CE: IN std_logic; 
    SINE: OUT std_logic_VECTOR(15 downto 0); 
    COSINE: OUT std_logic_VECTOR(15 downto 0)); 
end component; 
 
 
  
------------------------------------------------------------- 
  
-- The following code must appear in the VHDL architecture body. 
-- Substitute your own instance name and net names. 
  
your_instance_name : ddsqam 
        port map ( 
            DATA => DATA, 
            WE => WE, 
            A => A, 
            CLK => CLK, 
            CE => CE, 
            SINE => SINE, 
            COSINE => COSINE); 
  
		</Template> 
	</Folder> 
</RootFolder>