www.pudn.com > 16QAM_verilog.rar > qam16_tb.v, change:2011-07-14,size:3775b


`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   22:18:01 07/13/2011
// Design Name:   qam16
// Module Name:   E:/HDL_Program/Verilog/DPD_related/qam16_yinweiqiu/qam16_prj/qam16_tb.v
// Project Name:  qam16_prj
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: qam16
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module qam16_tb;

	// Inputs
	reg clk;
	reg clk12p5MHz;
	reg reset;
	reg x;

	// Outputs
	wire [17:0] y; 

	// parameters
	parameter clk_period = 10000; // 10us
	parameter clk12p5MHz_period = 80; // 80ns
	
	// Instantiate the Unit Under Test (UUT)
	qam16 uut (
		.clk(clk), 
		.clk12p5MHz(clk12p5MHz), 
		.reset(reset), 
		.x(x), 
		.y(y)
	);

	initial begin
		// Initialize clock signal
		clk = 0;
		clk12p5MHz = 0;
	end
    
	initial begin
		// Initialize reset signal,active low
		reset = 1;
		// Wait 100 ns for global reset to finish
		#(3*clk_period);
		reset = 0;
		#(3*clk_period);
        reset = 1;
	end
		
	initial begin
		// Initialize Inputs x;
		x = 0; 
		#(clk_period); 
		// x_t = 4'b0000 
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 0; 
		// x_t = 4'b0001 
		#(clk_period) x = 0; 
		#(clk_period) x = 0; 
		#(clk_period) x = 0; 
		#(clk_period) x = 1; 
		// x_t = 4'b0010 
		#(clk_period) x = 0; 
		#(clk_period) x = 0; 
		#(clk_period) x = 1; 
		#(clk_period) x = 0; 
		// x_t = 4'b0011 
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 1; 
		// x_t = 4'b0100
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 0; 
		// x_t = 4'b0101
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 1; 
		// x_t = 4'b0110
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 0; 
		// x_t = 4'b0111
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 1; 
		// x_t = 4'b1000
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 0; 
		// x_t = 4'b1001
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 1; 
		// x_t = 4'b1010
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 0; 
		// x_t = 4'b1011
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 1; 
		// x_t = 4'b1100
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 0; 
		// x_t = 4'b1101
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 1; 
		// x_t = 4'b1110
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 0; 
		// x_t = 4'b1111
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		#(clk_period) x = 1; 
		// x_t = 4'b0000
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		// x_t = 4'b0001
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		// x_t = 4'b0010
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		// x_t = 4'b0011
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 1;
		// x_t = 4'b0100
		#(clk_period) x = 0;
		#(clk_period) x = 1;
		#(clk_period) x = 0;
		#(clk_period) x = 0;
		$stop;
	end
	
	always # (clk_period/2) clk = ~clk;
	always # (clk12p5MHz_period/2) clk12p5MHz = ~clk12p5MHz;
	
endmodule