www.pudn.com > 16QAM_verilog.rar > ddsqam_readme.txt, change:2011-07-13,size:2122b


The following files were generated for 'ddsqam' in directory  
E:\HDL_Program\Verilog\DPD_related\qam16_yinweiqiu\qam16_right_prj: 
 
ddsqam.asy: 
   Graphical symbol information file. Used by the ISE tools and some 
   third party tools to create a symbol representing the core. 
 
ddsqam.edn: 
   Electronic Data Netlist (EDN) file containing the information 
   required to implement the module in a Xilinx (R) FPGA. 
 
ddsqam.sym: 
   Please see the core data sheet. 
 
ddsqam.v: 
   Verilog wrapper file provided to support functional simulation. 
   This file contains simulation model customization data that is 
   passed to a parameterized simulation model for the core. 
 
ddsqam.veo: 
   VEO template file containing code that can be used as a model for 
   instantiating a CORE Generator module in a Verilog design. 
 
ddsqam.vhd: 
   VHDL wrapper file provided to support functional simulation. This 
   file contains simulation model customization data that is passed to 
   a parameterized simulation model for the core. 
 
ddsqam.vho: 
   VHO template file containing code that can be used as a model for 
   instantiating a CORE Generator module in a VHDL design. 
 
ddsqam.xco: 
   CORE Generator input file containing the parameters used to 
   regenerate a core. 
 
ddsqam_SINCOS_TABLE_TRIG_ROM.mif: 
   Memory Initialization File which is automatically generated by the 
   CORE Generator System for some modules when a simulation flow is 
   specified. A MIF data file is used to support HDL functional 
   simulation of modules which use arrays of values. 
 
ddsqam_flist.txt: 
   Text file listing all of the output files produced when a customized 
   core was generated in the CORE Generator. 
 
ddsqam_readme.txt: 
   Text file indicating the files generated and how they are used. 
 
ddsqam_xmdf.tcl: 
   ISE Project Navigator interface file. ISE uses this file to determine 
   how the files output by CORE Generator for the core can be integrated 
   into your ISE project. 
 
 
Please see the Xilinx CORE Generator online help for further details on 
generated files and how to use them.