www.pudn.com > 16QAM_verilog.rar > ddsqam.xco, change:2011-07-13,size:1709b


##############################################################
#
# Xilinx Core Generator version K.39
# Date: Wed Jul 13 15:19:51 2011
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc2vp2
SET devicefamily = virtex2p
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Edif
SET package = fg256
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -7
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Direct_Digital_Synthesizer family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET accumulator_latency=One_Cycle
CSET aclr_pin=false
CSET channel_pin=false
CSET channels=1
CSET clock_enable=true
CSET component_name=ddsqam
CSET create_rpm=false
CSET dds_clock_rate=12.5
CSET frequency_resolution=0.4
CSET memory_type=Auto
CSET negative_cosine=false
CSET negative_sine=false
CSET noise_shaping=Auto
CSET output_frequencies=0.0
CSET outputs_required=Sine_and_Cosine
CSET phase_increment=Programmable
CSET phase_offset=None
CSET phase_offset_angles=0.0
CSET pipelined=true
CSET rdy_pin=false
CSET rfd_pin=false
CSET sclr_pin=false
CSET spurious_free_dynamic_range=96.0
# END Parameters
GENERATE
# CRC: 1930a341