www.pudn.com > 16QAM_verilog.rar > ddsqam.vho, change:2011-07-13,size:3589b


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-- The following code must appear in the VHDL architecture header: 
 
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 
component ddsqam 
	port ( 
	DATA: IN std_logic_VECTOR(24 downto 0); 
	WE: IN std_logic; 
	A: IN std_logic_VECTOR(4 downto 0); 
	CLK: IN std_logic; 
	CE: IN std_logic; 
	SINE: OUT std_logic_VECTOR(15 downto 0); 
	COSINE: OUT std_logic_VECTOR(15 downto 0)); 
end component; 
 
-- Synplicity black box declaration 
attribute syn_black_box : boolean; 
attribute syn_black_box of ddsqam: component is true; 
 
-- COMP_TAG_END ------ End COMPONENT Declaration ------------ 
 
-- The following code must appear in the VHDL architecture 
-- body. Substitute your own instance name and net names. 
 
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 
your_instance_name : ddsqam 
		port map ( 
			DATA => DATA, 
			WE => WE, 
			A => A, 
			CLK => CLK, 
			CE => CE, 
			SINE => SINE, 
			COSINE => COSINE); 
-- INST_TAG_END ------ End INSTANTIATION Template ------------ 
 
-- You must compile the wrapper file ddsqam.vhd when simulating 
-- the core, ddsqam. When compiling the wrapper file, be sure to 
-- reference the XilinxCoreLib VHDL simulation library. For detailed 
-- instructions, please refer to the "CORE Generator Help".