www.pudn.com > 16QAM_verilog.rar > ddsqam.vhd, change:2011-07-13,size:79668b


-------------------------------------------------------------------------------- 
--     This file is owned and controlled by Xilinx and must be used           -- 
--     solely for design, simulation, implementation and creation of          -- 
--     design files limited to Xilinx devices or technologies. Use            -- 
--     with non-Xilinx devices or technologies is expressly prohibited        -- 
--     and immediately terminates your license.                               -- 
--                                                                            -- 
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          -- 
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                -- 
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        -- 
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            -- 
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              -- 
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                -- 
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       -- 
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               -- 
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                -- 
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         -- 
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        -- 
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        -- 
--     FOR A PARTICULAR PURPOSE.                                              -- 
--                                                                            -- 
--     Xilinx products are not intended for use in life support               -- 
--     appliances, devices, or systems. Use in such applications are          -- 
--     expressly prohibited.                                                  -- 
--                                                                            -- 
--     (c) Copyright 1995-2007 Xilinx, Inc.                                   -- 
--     All rights reserved.                                                   -- 
-------------------------------------------------------------------------------- 
 
-- synthesis translate_off 
LIBRARY std, ieee; 
USE std.standard.ALL; 
USE ieee.std_logic_1164.ALL; 
 
LIBRARY unisim; 
USE unisim.vcomponents.ALL; 
 
 
LIBRARY XilinxCoreLib; 
USE XilinxCoreLib.c_compare_v7_0_comp.ALL; 
USE XilinxCoreLib.c_shift_ram_v7_0_comp.ALL; 
USE XilinxCoreLib.c_reg_fd_v7_0_comp.ALL; 
USE XilinxCoreLib.blkmemdp_v6_0_comp.ALL; 
USE XilinxCoreLib.c_twos_comp_v7_0_comp.ALL; 
USE XilinxCoreLib.c_gate_bit_v7_0_comp.ALL; 
USE XilinxCoreLib.c_shift_fd_v7_0_comp.ALL; 
USE XilinxCoreLib.c_addsub_v7_0_comp.ALL; 
 
ENTITY ddsqam IS 
   PORT ( 
      DATA : IN STD_LOGIC_VECTOR(24 DOWNTO 0); 
      WE : IN STD_LOGIC; 
      A : IN STD_LOGIC_VECTOR(4 DOWNTO 0); 
      CLK : IN STD_LOGIC; 
      CE : IN STD_LOGIC; 
      SINE : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 
      COSINE : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)    
); 
END ddsqam; 
 
ARCHITECTURE xilinx OF ddsqam IS  
 
-- Signals for connecting to instantiations 
   SIGNAL BU2_I : STD_LOGIC_VECTOR(5 DOWNTO 0); 
   SIGNAL BU2_T : STD_LOGIC; 
   SIGNAL BU2_EN : STD_LOGIC; 
   SIGNAL BU2_Q : STD_LOGIC; 
   SIGNAL BU2_CLK : STD_LOGIC; 
   SIGNAL BU2_CE : STD_LOGIC; 
   SIGNAL BU2_ACLR : STD_LOGIC; 
   SIGNAL BU2_ASET : STD_LOGIC; 
   SIGNAL BU2_AINIT : STD_LOGIC; 
   SIGNAL BU2_SCLR : STD_LOGIC; 
   SIGNAL BU2_SSET : STD_LOGIC; 
   SIGNAL BU2_SINIT : STD_LOGIC; 
   SIGNAL BU2_O : STD_LOGIC; 
   SIGNAL BU12_D : STD_LOGIC_VECTOR(24 DOWNTO 0); 
   SIGNAL BU12_Q : STD_LOGIC_VECTOR(24 DOWNTO 0); 
   SIGNAL BU12_CLK : STD_LOGIC; 
   SIGNAL BU12_CE : STD_LOGIC; 
   SIGNAL BU64_A : STD_LOGIC_VECTOR(24 DOWNTO 0); 
   SIGNAL BU64_B : STD_LOGIC_VECTOR(24 DOWNTO 0); 
   SIGNAL BU64_Q : STD_LOGIC_VECTOR(24 DOWNTO 0); 
   SIGNAL BU64_CLK : STD_LOGIC; 
   SIGNAL BU64_CE : STD_LOGIC; 
   SIGNAL BU214_CLK : STD_LOGIC; 
   SIGNAL BU214_SDOUT : STD_LOGIC; 
   SIGNAL BU214_CE : STD_LOGIC; 
   SIGNAL BU538_A : STD_LOGIC_VECTOR(22 DOWNTO 0); 
   SIGNAL BU538_B : STD_LOGIC_VECTOR(9 DOWNTO 0); 
   SIGNAL BU538_Q : STD_LOGIC_VECTOR(13 DOWNTO 0); 
   SIGNAL BU538_CLK : STD_LOGIC; 
   SIGNAL BU538_CE : STD_LOGIC; 
   SIGNAL BU477_A : STD_LOGIC_VECTOR(8 DOWNTO 0); 
   SIGNAL BU477_B : STD_LOGIC_VECTOR(8 DOWNTO 0); 
   SIGNAL BU477_Q : STD_LOGIC_VECTOR(9 DOWNTO 0); 
   SIGNAL BU477_CLK : STD_LOGIC; 
   SIGNAL BU477_CE : STD_LOGIC; 
   SIGNAL BU291_A : STD_LOGIC_VECTOR(7 DOWNTO 0); 
   SIGNAL BU291_B : STD_LOGIC_VECTOR(7 DOWNTO 0); 
   SIGNAL BU291_Q : STD_LOGIC_VECTOR(8 DOWNTO 0); 
   SIGNAL BU291_CLK : STD_LOGIC; 
   SIGNAL BU291_CE : STD_LOGIC; 
   SIGNAL BU222_I : STD_LOGIC_VECTOR(3 DOWNTO 0); 
   SIGNAL BU222_T : STD_LOGIC; 
   SIGNAL BU222_EN : STD_LOGIC; 
   SIGNAL BU222_Q : STD_LOGIC; 
   SIGNAL BU222_CLK : STD_LOGIC; 
   SIGNAL BU222_CE : STD_LOGIC; 
   SIGNAL BU222_ACLR : STD_LOGIC; 
   SIGNAL BU222_ASET : STD_LOGIC; 
   SIGNAL BU222_AINIT : STD_LOGIC; 
   SIGNAL BU222_SCLR : STD_LOGIC; 
   SIGNAL BU222_SSET : STD_LOGIC; 
   SIGNAL BU222_SINIT : STD_LOGIC; 
   SIGNAL BU222_O : STD_LOGIC; 
   SIGNAL BU227_CLK : STD_LOGIC; 
   SIGNAL BU227_SDIN : STD_LOGIC; 
   SIGNAL BU227_Q : STD_LOGIC_VECTOR(12 DOWNTO 0); 
   SIGNAL BU227_CE : STD_LOGIC; 
   SIGNAL BU256_I : STD_LOGIC_VECTOR(3 DOWNTO 0); 
   SIGNAL BU256_T : STD_LOGIC; 
   SIGNAL BU256_EN : STD_LOGIC; 
   SIGNAL BU256_Q : STD_LOGIC; 
   SIGNAL BU256_CLK : STD_LOGIC; 
   SIGNAL BU256_CE : STD_LOGIC; 
   SIGNAL BU256_ACLR : STD_LOGIC; 
   SIGNAL BU256_ASET : STD_LOGIC; 
   SIGNAL BU256_AINIT : STD_LOGIC; 
   SIGNAL BU256_SCLR : STD_LOGIC; 
   SIGNAL BU256_SSET : STD_LOGIC; 
   SIGNAL BU256_SINIT : STD_LOGIC; 
   SIGNAL BU256_O : STD_LOGIC; 
   SIGNAL BU261_CLK : STD_LOGIC; 
   SIGNAL BU261_SDIN : STD_LOGIC; 
   SIGNAL BU261_Q : STD_LOGIC_VECTOR(13 DOWNTO 0); 
   SIGNAL BU261_CE : STD_LOGIC; 
   SIGNAL BU423_A : STD_LOGIC_VECTOR(7 DOWNTO 0); 
   SIGNAL BU423_B : STD_LOGIC_VECTOR(7 DOWNTO 0); 
   SIGNAL BU423_Q : STD_LOGIC_VECTOR(8 DOWNTO 0); 
   SIGNAL BU423_CLK : STD_LOGIC; 
   SIGNAL BU423_CE : STD_LOGIC; 
   SIGNAL BU346_I : STD_LOGIC_VECTOR(1 DOWNTO 0); 
   SIGNAL BU346_T : STD_LOGIC; 
   SIGNAL BU346_EN : STD_LOGIC; 
   SIGNAL BU346_Q : STD_LOGIC; 
   SIGNAL BU346_CLK : STD_LOGIC; 
   SIGNAL BU346_CE : STD_LOGIC; 
   SIGNAL BU346_ACLR : STD_LOGIC; 
   SIGNAL BU346_ASET : STD_LOGIC; 
   SIGNAL BU346_AINIT : STD_LOGIC; 
   SIGNAL BU346_SCLR : STD_LOGIC; 
   SIGNAL BU346_SSET : STD_LOGIC; 
   SIGNAL BU346_SINIT : STD_LOGIC; 
   SIGNAL BU346_O : STD_LOGIC; 
   SIGNAL BU351_CLK : STD_LOGIC; 
   SIGNAL BU351_SDIN : STD_LOGIC; 
   SIGNAL BU351_Q : STD_LOGIC_VECTOR(14 DOWNTO 0); 
   SIGNAL BU351_CE : STD_LOGIC; 
   SIGNAL BU384_I : STD_LOGIC_VECTOR(3 DOWNTO 0); 
   SIGNAL BU384_T : STD_LOGIC; 
   SIGNAL BU384_EN : STD_LOGIC; 
   SIGNAL BU384_Q : STD_LOGIC; 
   SIGNAL BU384_CLK : STD_LOGIC; 
   SIGNAL BU384_CE : STD_LOGIC; 
   SIGNAL BU384_ACLR : STD_LOGIC; 
   SIGNAL BU384_ASET : STD_LOGIC; 
   SIGNAL BU384_AINIT : STD_LOGIC; 
   SIGNAL BU384_SCLR : STD_LOGIC; 
   SIGNAL BU384_SSET : STD_LOGIC; 
   SIGNAL BU384_SINIT : STD_LOGIC; 
   SIGNAL BU384_O : STD_LOGIC; 
   SIGNAL BU389_CLK : STD_LOGIC; 
   SIGNAL BU389_SDIN : STD_LOGIC; 
   SIGNAL BU389_Q : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU389_CE : STD_LOGIC; 
   SIGNAL BU742_D : STD_LOGIC_VECTOR(13 DOWNTO 0); 
   SIGNAL BU742_Q : STD_LOGIC_VECTOR(13 DOWNTO 0); 
   SIGNAL BU742_CLK : STD_LOGIC; 
   SIGNAL BU742_CE : STD_LOGIC; 
   SIGNAL BU773_A : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU773_BYPASS : STD_LOGIC; 
   SIGNAL BU773_CLK : STD_LOGIC; 
   SIGNAL BU773_Q : STD_LOGIC_VECTOR(12 DOWNTO 0); 
   SIGNAL BU773_CE : STD_LOGIC; 
   SIGNAL BU866_CLK : STD_LOGIC; 
   SIGNAL BU866_D : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU866_Q : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU866_CE : STD_LOGIC; 
   SIGNAL BU874_CLK : STD_LOGIC; 
   SIGNAL BU874_D : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU874_Q : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU874_CE : STD_LOGIC; 
   SIGNAL BU885_I0 : STD_LOGIC; 
   SIGNAL BU885_I1 : STD_LOGIC; 
   SIGNAL BU885_I2 : STD_LOGIC; 
   SIGNAL BU885_I3 : STD_LOGIC; 
   SIGNAL BU885_O : STD_LOGIC; 
   SIGNAL BU886_D : STD_LOGIC; 
   SIGNAL BU886_C : STD_LOGIC; 
   SIGNAL BU886_CE : STD_LOGIC; 
   SIGNAL BU886_PRE : STD_LOGIC; 
   SIGNAL BU886_Q : STD_LOGIC; 
   SIGNAL BU890_I0 : STD_LOGIC; 
   SIGNAL BU890_I1 : STD_LOGIC; 
   SIGNAL BU890_I2 : STD_LOGIC; 
   SIGNAL BU890_I3 : STD_LOGIC; 
   SIGNAL BU890_O : STD_LOGIC; 
   SIGNAL BU891_D : STD_LOGIC; 
   SIGNAL BU891_C : STD_LOGIC; 
   SIGNAL BU891_CE : STD_LOGIC; 
   SIGNAL BU891_Q : STD_LOGIC; 
   SIGNAL BU895_I0 : STD_LOGIC; 
   SIGNAL BU895_I1 : STD_LOGIC; 
   SIGNAL BU895_I2 : STD_LOGIC; 
   SIGNAL BU895_I3 : STD_LOGIC; 
   SIGNAL BU895_O : STD_LOGIC; 
   SIGNAL BU896_D : STD_LOGIC; 
   SIGNAL BU896_C : STD_LOGIC; 
   SIGNAL BU896_CE : STD_LOGIC; 
   SIGNAL BU896_Q : STD_LOGIC; 
   SIGNAL BU898_A : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU898_CLK : STD_LOGIC; 
   SIGNAL BU898_CE : STD_LOGIC; 
   SIGNAL BU898_ACLR : STD_LOGIC; 
   SIGNAL BU898_QA_GE_B : STD_LOGIC; 
   SIGNAL BU940_A : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU940_CLK : STD_LOGIC; 
   SIGNAL BU940_CE : STD_LOGIC; 
   SIGNAL BU940_ACLR : STD_LOGIC; 
   SIGNAL BU940_QA_EQ_B : STD_LOGIC; 
   SIGNAL BU959_D : STD_LOGIC_VECTOR(13 DOWNTO 0); 
   SIGNAL BU959_Q : STD_LOGIC_VECTOR(13 DOWNTO 0); 
   SIGNAL BU959_CLK : STD_LOGIC; 
   SIGNAL BU959_CE : STD_LOGIC; 
   SIGNAL BU990_A : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU990_BYPASS : STD_LOGIC; 
   SIGNAL BU990_CLK : STD_LOGIC; 
   SIGNAL BU990_Q : STD_LOGIC_VECTOR(12 DOWNTO 0); 
   SIGNAL BU990_CE : STD_LOGIC; 
   SIGNAL BU1085_CLK : STD_LOGIC; 
   SIGNAL BU1085_D : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU1085_Q : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU1085_CE : STD_LOGIC; 
   SIGNAL BU1093_CLK : STD_LOGIC; 
   SIGNAL BU1093_D : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU1093_Q : STD_LOGIC_VECTOR(0 DOWNTO 0); 
   SIGNAL BU1093_CE : STD_LOGIC; 
   SIGNAL BU1104_I0 : STD_LOGIC; 
   SIGNAL BU1104_I1 : STD_LOGIC; 
   SIGNAL BU1104_I2 : STD_LOGIC; 
   SIGNAL BU1104_I3 : STD_LOGIC; 
   SIGNAL BU1104_O : STD_LOGIC; 
   SIGNAL BU1105_D : STD_LOGIC; 
   SIGNAL BU1105_C : STD_LOGIC; 
   SIGNAL BU1105_CE : STD_LOGIC; 
   SIGNAL BU1105_PRE : STD_LOGIC; 
   SIGNAL BU1105_Q : STD_LOGIC; 
   SIGNAL BU1109_I0 : STD_LOGIC; 
   SIGNAL BU1109_I1 : STD_LOGIC; 
   SIGNAL BU1109_I2 : STD_LOGIC; 
   SIGNAL BU1109_I3 : STD_LOGIC; 
   SIGNAL BU1109_O : STD_LOGIC; 
   SIGNAL BU1110_D : STD_LOGIC; 
   SIGNAL BU1110_C : STD_LOGIC; 
   SIGNAL BU1110_CE : STD_LOGIC; 
   SIGNAL BU1110_Q : STD_LOGIC; 
   SIGNAL BU1114_I0 : STD_LOGIC; 
   SIGNAL BU1114_I1 : STD_LOGIC; 
   SIGNAL BU1114_I2 : STD_LOGIC; 
   SIGNAL BU1114_I3 : STD_LOGIC; 
   SIGNAL BU1114_O : STD_LOGIC; 
   SIGNAL BU1115_D : STD_LOGIC; 
   SIGNAL BU1115_C : STD_LOGIC; 
   SIGNAL BU1115_CE : STD_LOGIC; 
   SIGNAL BU1115_Q : STD_LOGIC; 
   SIGNAL BU1117_A : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU1117_CLK : STD_LOGIC; 
   SIGNAL BU1117_CE : STD_LOGIC; 
   SIGNAL BU1117_ACLR : STD_LOGIC; 
   SIGNAL BU1117_QA_GE_B : STD_LOGIC; 
   SIGNAL BU1159_A : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU1159_CLK : STD_LOGIC; 
   SIGNAL BU1159_CE : STD_LOGIC; 
   SIGNAL BU1159_ACLR : STD_LOGIC; 
   SIGNAL BU1159_QA_EQ_B : STD_LOGIC; 
   SIGNAL BU652_addra : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU652_addrb : STD_LOGIC_VECTOR(11 DOWNTO 0); 
   SIGNAL BU652_clka : STD_LOGIC; 
   SIGNAL BU652_clkb : STD_LOGIC; 
   SIGNAL BU652_dina : STD_LOGIC_VECTOR(14 DOWNTO 0); 
   SIGNAL BU652_dinb : STD_LOGIC_VECTOR(14 DOWNTO 0); 
   SIGNAL BU652_douta : STD_LOGIC_VECTOR(14 DOWNTO 0); 
   SIGNAL BU652_doutb : STD_LOGIC_VECTOR(14 DOWNTO 0); 
   SIGNAL BU652_ena : STD_LOGIC; 
   SIGNAL BU652_enb : STD_LOGIC; 
   SIGNAL BU652_nda : STD_LOGIC; 
   SIGNAL BU652_ndb : STD_LOGIC; 
   SIGNAL BU652_rfda : STD_LOGIC; 
   SIGNAL BU652_rfdb : STD_LOGIC; 
   SIGNAL BU652_rdya : STD_LOGIC; 
   SIGNAL BU652_rdyb : STD_LOGIC; 
   SIGNAL BU652_sinita : STD_LOGIC; 
   SIGNAL BU652_sinitb : STD_LOGIC; 
   SIGNAL BU652_wea : STD_LOGIC; 
   SIGNAL BU652_web : STD_LOGIC; 
   SIGNAL BU1178_A : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU1178_B : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU1178_C_IN : STD_LOGIC; 
   SIGNAL BU1178_ADD : STD_LOGIC; 
   SIGNAL BU1178_Q : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU1178_CLK : STD_LOGIC; 
   SIGNAL BU1178_CE : STD_LOGIC; 
   SIGNAL BU1275_CLK : STD_LOGIC; 
   SIGNAL BU1275_SDIN : STD_LOGIC; 
   SIGNAL BU1275_SDOUT : STD_LOGIC; 
   SIGNAL BU1275_CE : STD_LOGIC; 
   SIGNAL BU1287_I0 : STD_LOGIC; 
   SIGNAL BU1287_I1 : STD_LOGIC; 
   SIGNAL BU1287_I2 : STD_LOGIC; 
   SIGNAL BU1287_I3 : STD_LOGIC; 
   SIGNAL BU1287_O : STD_LOGIC; 
   SIGNAL BU1290_A : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU1290_B : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU1290_C_IN : STD_LOGIC; 
   SIGNAL BU1290_ADD : STD_LOGIC; 
   SIGNAL BU1290_Q : STD_LOGIC_VECTOR(15 DOWNTO 0); 
   SIGNAL BU1290_CLK : STD_LOGIC; 
   SIGNAL BU1290_CE : STD_LOGIC; 
   SIGNAL n0 : STD_LOGIC := '0'; 
   SIGNAL n1 : STD_LOGIC := '1'; 
   SIGNAL n2 : STD_LOGIC; 
   SIGNAL n3 : STD_LOGIC; 
   SIGNAL n4 : STD_LOGIC; 
   SIGNAL n5 : STD_LOGIC; 
   SIGNAL n6 : STD_LOGIC; 
   SIGNAL n7 : STD_LOGIC; 
   SIGNAL n8 : STD_LOGIC; 
   SIGNAL n19 : STD_LOGIC; 
   SIGNAL n20 : STD_LOGIC; 
   SIGNAL n21 : STD_LOGIC; 
   SIGNAL n22 : STD_LOGIC; 
   SIGNAL n23 : STD_LOGIC; 
   SIGNAL n24 : STD_LOGIC; 
   SIGNAL n25 : STD_LOGIC; 
   SIGNAL n26 : STD_LOGIC; 
   SIGNAL n27 : STD_LOGIC; 
   SIGNAL n28 : STD_LOGIC; 
   SIGNAL n29 : STD_LOGIC; 
   SIGNAL n30 : STD_LOGIC; 
   SIGNAL n31 : STD_LOGIC; 
   SIGNAL n32 : STD_LOGIC; 
   SIGNAL n33 : STD_LOGIC; 
   SIGNAL n34 : STD_LOGIC; 
   SIGNAL n35 : STD_LOGIC; 
   SIGNAL n36 : STD_LOGIC; 
   SIGNAL n37 : STD_LOGIC; 
   SIGNAL n38 : STD_LOGIC; 
   SIGNAL n39 : STD_LOGIC; 
   SIGNAL n40 : STD_LOGIC; 
   SIGNAL n41 : STD_LOGIC; 
   SIGNAL n42 : STD_LOGIC; 
   SIGNAL n43 : STD_LOGIC; 
   SIGNAL n44 : STD_LOGIC; 
   SIGNAL n45 : STD_LOGIC; 
   SIGNAL n46 : STD_LOGIC; 
   SIGNAL n47 : STD_LOGIC; 
   SIGNAL n48 : STD_LOGIC; 
   SIGNAL n49 : STD_LOGIC; 
   SIGNAL n50 : STD_LOGIC; 
   SIGNAL n51 : STD_LOGIC; 
   SIGNAL n52 : STD_LOGIC; 
   SIGNAL n53 : STD_LOGIC; 
   SIGNAL n54 : STD_LOGIC; 
   SIGNAL n55 : STD_LOGIC; 
   SIGNAL n56 : STD_LOGIC; 
   SIGNAL n57 : STD_LOGIC; 
   SIGNAL n58 : STD_LOGIC; 
   SIGNAL n59 : STD_LOGIC; 
   SIGNAL n60 : STD_LOGIC; 
   SIGNAL n61 : STD_LOGIC; 
   SIGNAL n62 : STD_LOGIC; 
   SIGNAL n63 : STD_LOGIC; 
   SIGNAL n64 : STD_LOGIC; 
   SIGNAL n65 : STD_LOGIC; 
   SIGNAL n66 : STD_LOGIC; 
   SIGNAL n67 : STD_LOGIC; 
   SIGNAL n68 : STD_LOGIC; 
   SIGNAL n102 : STD_LOGIC; 
   SIGNAL n103 : STD_LOGIC; 
   SIGNAL n104 : STD_LOGIC; 
   SIGNAL n105 : STD_LOGIC; 
   SIGNAL n106 : STD_LOGIC; 
   SIGNAL n107 : STD_LOGIC; 
   SIGNAL n108 : STD_LOGIC; 
   SIGNAL n109 : STD_LOGIC; 
   SIGNAL n110 : STD_LOGIC; 
   SIGNAL n111 : STD_LOGIC; 
   SIGNAL n112 : STD_LOGIC; 
   SIGNAL n113 : STD_LOGIC; 
   SIGNAL n114 : STD_LOGIC; 
   SIGNAL n115 : STD_LOGIC; 
   SIGNAL n116 : STD_LOGIC; 
   SIGNAL n117 : STD_LOGIC; 
   SIGNAL n118 : STD_LOGIC; 
   SIGNAL n119 : STD_LOGIC; 
   SIGNAL n120 : STD_LOGIC; 
   SIGNAL n121 : STD_LOGIC; 
   SIGNAL n122 : STD_LOGIC; 
   SIGNAL n123 : STD_LOGIC; 
   SIGNAL n124 : STD_LOGIC; 
   SIGNAL n125 : STD_LOGIC; 
   SIGNAL n126 : STD_LOGIC; 
   SIGNAL n133 : STD_LOGIC; 
   SIGNAL n134 : STD_LOGIC; 
   SIGNAL n135 : STD_LOGIC; 
   SIGNAL n136 : STD_LOGIC; 
   SIGNAL n137 : STD_LOGIC; 
   SIGNAL n138 : STD_LOGIC; 
   SIGNAL n139 : STD_LOGIC; 
   SIGNAL n140 : STD_LOGIC; 
   SIGNAL n141 : STD_LOGIC; 
   SIGNAL n142 : STD_LOGIC; 
   SIGNAL n143 : STD_LOGIC; 
   SIGNAL n144 : STD_LOGIC; 
   SIGNAL n145 : STD_LOGIC; 
   SIGNAL n146 : STD_LOGIC; 
   SIGNAL n147 : STD_LOGIC; 
   SIGNAL n148 : STD_LOGIC; 
   SIGNAL n149 : STD_LOGIC; 
   SIGNAL n150 : STD_LOGIC; 
   SIGNAL n151 : STD_LOGIC; 
   SIGNAL n152 : STD_LOGIC; 
   SIGNAL n153 : STD_LOGIC; 
   SIGNAL n154 : STD_LOGIC; 
   SIGNAL n155 : STD_LOGIC; 
   SIGNAL n156 : STD_LOGIC; 
   SIGNAL n157 : STD_LOGIC; 
   SIGNAL n158 : STD_LOGIC; 
   SIGNAL n159 : STD_LOGIC; 
   SIGNAL n160 : STD_LOGIC; 
   SIGNAL n161 : STD_LOGIC; 
   SIGNAL n162 : STD_LOGIC; 
   SIGNAL n163 : STD_LOGIC; 
   SIGNAL n164 : STD_LOGIC; 
   SIGNAL n165 : STD_LOGIC; 
   SIGNAL n166 : STD_LOGIC; 
   SIGNAL n216 : STD_LOGIC; 
   SIGNAL n217 : STD_LOGIC; 
   SIGNAL n218 : STD_LOGIC; 
   SIGNAL n219 : STD_LOGIC; 
   SIGNAL n220 : STD_LOGIC; 
   SIGNAL n221 : STD_LOGIC; 
   SIGNAL n222 : STD_LOGIC; 
   SIGNAL n223 : STD_LOGIC; 
   SIGNAL n224 : STD_LOGIC; 
   SIGNAL n225 : STD_LOGIC; 
   SIGNAL n226 : STD_LOGIC; 
   SIGNAL n227 : STD_LOGIC; 
   SIGNAL n228 : STD_LOGIC; 
   SIGNAL n229 : STD_LOGIC; 
   SIGNAL n230 : STD_LOGIC; 
   SIGNAL n231 : STD_LOGIC; 
   SIGNAL n232 : STD_LOGIC; 
   SIGNAL n233 : STD_LOGIC; 
   SIGNAL n234 : STD_LOGIC; 
   SIGNAL n235 : STD_LOGIC; 
   SIGNAL n236 : STD_LOGIC; 
   SIGNAL n237 : STD_LOGIC; 
   SIGNAL n238 : STD_LOGIC; 
   SIGNAL n239 : STD_LOGIC; 
   SIGNAL n240 : STD_LOGIC; 
   SIGNAL n1014 : STD_LOGIC; 
   SIGNAL n1015 : STD_LOGIC; 
   SIGNAL n1016 : STD_LOGIC; 
   SIGNAL n1017 : STD_LOGIC; 
   SIGNAL n1018 : STD_LOGIC; 
   SIGNAL n1019 : STD_LOGIC; 
   SIGNAL n1020 : STD_LOGIC; 
   SIGNAL n1021 : STD_LOGIC; 
   SIGNAL n1022 : STD_LOGIC; 
   SIGNAL n1023 : STD_LOGIC; 
   SIGNAL n1024 : STD_LOGIC; 
   SIGNAL n1025 : STD_LOGIC; 
   SIGNAL n1064 : STD_LOGIC; 
   SIGNAL n1065 : STD_LOGIC; 
   SIGNAL n1066 : STD_LOGIC; 
   SIGNAL n1067 : STD_LOGIC; 
   SIGNAL n1068 : STD_LOGIC; 
   SIGNAL n1069 : STD_LOGIC; 
   SIGNAL n1070 : STD_LOGIC; 
   SIGNAL n1071 : STD_LOGIC; 
   SIGNAL n1072 : STD_LOGIC; 
   SIGNAL n1073 : STD_LOGIC; 
   SIGNAL n1074 : STD_LOGIC; 
   SIGNAL n1115 : STD_LOGIC; 
   SIGNAL n1116 : STD_LOGIC; 
   SIGNAL n1117 : STD_LOGIC; 
   SIGNAL n1118 : STD_LOGIC; 
   SIGNAL n1119 : STD_LOGIC; 
   SIGNAL n1120 : STD_LOGIC; 
   SIGNAL n1121 : STD_LOGIC; 
   SIGNAL n1122 : STD_LOGIC; 
   SIGNAL n1123 : STD_LOGIC; 
   SIGNAL n1124 : STD_LOGIC; 
   SIGNAL n1125 : STD_LOGIC; 
   SIGNAL n1126 : STD_LOGIC; 
   SIGNAL n1127 : STD_LOGIC; 
   SIGNAL n1128 : STD_LOGIC; 
   SIGNAL n1129 : STD_LOGIC; 
   SIGNAL n1130 : STD_LOGIC; 
   SIGNAL n1131 : STD_LOGIC; 
   SIGNAL n1132 : STD_LOGIC; 
   SIGNAL n1133 : STD_LOGIC; 
   SIGNAL n1170 : STD_LOGIC; 
   SIGNAL n1171 : STD_LOGIC; 
   SIGNAL n1172 : STD_LOGIC; 
   SIGNAL n1173 : STD_LOGIC; 
   SIGNAL n1174 : STD_LOGIC; 
   SIGNAL n1175 : STD_LOGIC; 
   SIGNAL n1176 : STD_LOGIC; 
   SIGNAL n1177 : STD_LOGIC; 
   SIGNAL n1178 : STD_LOGIC; 
   SIGNAL n1179 : STD_LOGIC; 
   SIGNAL n1180 : STD_LOGIC; 
   SIGNAL n1223 : STD_LOGIC; 
   SIGNAL n1224 : STD_LOGIC; 
   SIGNAL n1225 : STD_LOGIC; 
   SIGNAL n1226 : STD_LOGIC; 
   SIGNAL n1227 : STD_LOGIC; 
   SIGNAL n1228 : STD_LOGIC; 
   SIGNAL n1229 : STD_LOGIC; 
   SIGNAL n1230 : STD_LOGIC; 
   SIGNAL n1231 : STD_LOGIC; 
   SIGNAL n1867 : STD_LOGIC; 
   SIGNAL n1868 : STD_LOGIC; 
   SIGNAL n1869 : STD_LOGIC; 
   SIGNAL n1870 : STD_LOGIC; 
   SIGNAL n1871 : STD_LOGIC; 
   SIGNAL n1872 : STD_LOGIC; 
   SIGNAL n1873 : STD_LOGIC; 
   SIGNAL n1874 : STD_LOGIC; 
   SIGNAL n1875 : STD_LOGIC; 
   SIGNAL n1876 : STD_LOGIC; 
   SIGNAL n1877 : STD_LOGIC; 
   SIGNAL n1878 : STD_LOGIC; 
   SIGNAL n1879 : STD_LOGIC; 
   SIGNAL n1880 : STD_LOGIC; 
   SIGNAL n1881 : STD_LOGIC; 
   SIGNAL n1882 : STD_LOGIC; 
   SIGNAL n1907 : STD_LOGIC; 
   SIGNAL n1908 : STD_LOGIC; 
   SIGNAL n1909 : STD_LOGIC; 
   SIGNAL n1910 : STD_LOGIC; 
   SIGNAL n1911 : STD_LOGIC; 
   SIGNAL n1912 : STD_LOGIC; 
   SIGNAL n1913 : STD_LOGIC; 
   SIGNAL n1914 : STD_LOGIC; 
   SIGNAL n1915 : STD_LOGIC; 
   SIGNAL n1916 : STD_LOGIC; 
   SIGNAL n1917 : STD_LOGIC; 
   SIGNAL n1918 : STD_LOGIC; 
   SIGNAL n1922 : STD_LOGIC; 
   SIGNAL n1923 : STD_LOGIC; 
   SIGNAL n1924 : STD_LOGIC; 
   SIGNAL n1925 : STD_LOGIC; 
   SIGNAL n1926 : STD_LOGIC; 
   SIGNAL n1927 : STD_LOGIC; 
   SIGNAL n1928 : STD_LOGIC; 
   SIGNAL n1929 : STD_LOGIC; 
   SIGNAL n1930 : STD_LOGIC; 
   SIGNAL n1931 : STD_LOGIC; 
   SIGNAL n1932 : STD_LOGIC; 
   SIGNAL n1933 : STD_LOGIC; 
   SIGNAL n1934 : STD_LOGIC; 
   SIGNAL n1935 : STD_LOGIC; 
   SIGNAL n1936 : STD_LOGIC; 
   SIGNAL n1937 : STD_LOGIC; 
   SIGNAL n1938 : STD_LOGIC; 
   SIGNAL n1939 : STD_LOGIC; 
   SIGNAL n1940 : STD_LOGIC; 
   SIGNAL n1941 : STD_LOGIC; 
   SIGNAL n1958 : STD_LOGIC; 
   SIGNAL n1959 : STD_LOGIC; 
   SIGNAL n1960 : STD_LOGIC; 
   SIGNAL n1961 : STD_LOGIC; 
   SIGNAL n1962 : STD_LOGIC; 
   SIGNAL n1963 : STD_LOGIC; 
   SIGNAL n1964 : STD_LOGIC; 
   SIGNAL n1965 : STD_LOGIC; 
   SIGNAL n1966 : STD_LOGIC; 
   SIGNAL n1967 : STD_LOGIC; 
   SIGNAL n1968 : STD_LOGIC; 
   SIGNAL n1969 : STD_LOGIC; 
   SIGNAL n1970 : STD_LOGIC; 
   SIGNAL n1971 : STD_LOGIC; 
   SIGNAL n1972 : STD_LOGIC; 
   SIGNAL n1973 : STD_LOGIC; 
   SIGNAL n1998 : STD_LOGIC; 
   SIGNAL n1999 : STD_LOGIC; 
   SIGNAL n2000 : STD_LOGIC; 
   SIGNAL n2001 : STD_LOGIC; 
   SIGNAL n2002 : STD_LOGIC; 
   SIGNAL n2003 : STD_LOGIC; 
   SIGNAL n2004 : STD_LOGIC; 
   SIGNAL n2005 : STD_LOGIC; 
   SIGNAL n2006 : STD_LOGIC; 
   SIGNAL n2007 : STD_LOGIC; 
   SIGNAL n2008 : STD_LOGIC; 
   SIGNAL n2009 : STD_LOGIC; 
   SIGNAL n2013 : STD_LOGIC; 
   SIGNAL n2014 : STD_LOGIC; 
   SIGNAL n2015 : STD_LOGIC; 
   SIGNAL n2016 : STD_LOGIC; 
   SIGNAL n2017 : STD_LOGIC; 
   SIGNAL n2018 : STD_LOGIC; 
   SIGNAL n2019 : STD_LOGIC; 
   SIGNAL n2020 : STD_LOGIC; 
   SIGNAL n2021 : STD_LOGIC; 
   SIGNAL n2022 : STD_LOGIC; 
   SIGNAL n2023 : STD_LOGIC; 
   SIGNAL n2024 : STD_LOGIC; 
   SIGNAL n2025 : STD_LOGIC; 
   SIGNAL n2026 : STD_LOGIC; 
   SIGNAL n2027 : STD_LOGIC; 
   SIGNAL n2028 : STD_LOGIC; 
   SIGNAL n2029 : STD_LOGIC; 
   SIGNAL n2030 : STD_LOGIC; 
   SIGNAL n2031 : STD_LOGIC; 
   SIGNAL n2032 : STD_LOGIC; 
   SIGNAL n2049 : STD_LOGIC; 
   SIGNAL n2067 : STD_LOGIC; 
   SIGNAL n2340 : STD_LOGIC; 
   SIGNAL n2359 : STD_LOGIC; 
   SIGNAL n2377 : STD_LOGIC; 
   SIGNAL n2659 : STD_LOGIC; 
   SIGNAL n2678 : STD_LOGIC; 
   SIGNAL n2696 : STD_LOGIC; 
 
BEGIN 
 
   n102 <= DATA(0); 
   n103 <= DATA(1); 
   n104 <= DATA(2); 
   n105 <= DATA(3); 
   n106 <= DATA(4); 
   n107 <= DATA(5); 
   n108 <= DATA(6); 
   n109 <= DATA(7); 
   n110 <= DATA(8); 
   n111 <= DATA(9); 
   n112 <= DATA(10); 
   n113 <= DATA(11); 
   n114 <= DATA(12); 
   n115 <= DATA(13); 
   n116 <= DATA(14); 
   n117 <= DATA(15); 
   n118 <= DATA(16); 
   n119 <= DATA(17); 
   n120 <= DATA(18); 
   n121 <= DATA(19); 
   n122 <= DATA(20); 
   n123 <= DATA(21); 
   n124 <= DATA(22); 
   n125 <= DATA(23); 
   n126 <= DATA(24); 
   n8 <= WE; 
   n3 <= A(0); 
   n4 <= A(1); 
   n5 <= A(2); 
   n6 <= A(3); 
   n7 <= A(4); 
   n133 <= CLK; 
   n134 <= CE; 
   SINE(0) <= n135; 
   SINE(1) <= n136; 
   SINE(2) <= n137; 
   SINE(3) <= n138; 
   SINE(4) <= n139; 
   SINE(5) <= n140; 
   SINE(6) <= n141; 
   SINE(7) <= n142; 
   SINE(8) <= n143; 
   SINE(9) <= n144; 
   SINE(10) <= n145; 
   SINE(11) <= n146; 
   SINE(12) <= n147; 
   SINE(13) <= n148; 
   SINE(14) <= n149; 
   SINE(15) <= n150; 
   COSINE(0) <= n151; 
   COSINE(1) <= n152; 
   COSINE(2) <= n153; 
   COSINE(3) <= n154; 
   COSINE(4) <= n155; 
   COSINE(5) <= n156; 
   COSINE(6) <= n157; 
   COSINE(7) <= n158; 
   COSINE(8) <= n159; 
   COSINE(9) <= n160; 
   COSINE(10) <= n161; 
   COSINE(11) <= n162; 
   COSINE(12) <= n163; 
   COSINE(13) <= n164; 
   COSINE(14) <= n165; 
   COSINE(15) <= n166; 
 
   BU2_I(0) <= n3; 
   BU2_I(1) <= n4; 
   BU2_I(2) <= n5; 
   BU2_I(3) <= n6; 
   BU2_I(4) <= n7; 
   BU2_I(5) <= n8; 
   BU2_T <= '0'; 
   BU2_EN <= '0'; 
   BU2_CLK <= '0'; 
   BU2_CE <= '0'; 
   BU2_ACLR <= '0'; 
   BU2_ASET <= '0'; 
   BU2_AINIT <= '0'; 
   BU2_SCLR <= '0'; 
   BU2_SSET <= '0'; 
   BU2_SINIT <= '0'; 
   n2 <= BU2_O; 
   BU2 : C_GATE_BIT_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_gate_type => 0, 
         c_sync_priority => 1, 
         c_has_sclr => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_pipe_stages => 0, 
         c_has_ce => 0, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_has_o => 1, 
         c_inputs => 6, 
         c_input_inv_mask => "011111" 
      ) 
      PORT MAP ( 
         I => BU2_I, 
         T => BU2_T, 
         EN => BU2_EN, 
         Q => BU2_Q, 
         CLK => BU2_CLK, 
         CE => BU2_CE, 
         ACLR => BU2_ACLR, 
         ASET => BU2_ASET, 
         AINIT => BU2_AINIT, 
         SCLR => BU2_SCLR, 
         SSET => BU2_SSET, 
         SINIT => BU2_SINIT, 
         O => BU2_O 
      ); 
 
   BU12_D(0) <= n102; 
   BU12_D(1) <= n103; 
   BU12_D(2) <= n104; 
   BU12_D(3) <= n105; 
   BU12_D(4) <= n106; 
   BU12_D(5) <= n107; 
   BU12_D(6) <= n108; 
   BU12_D(7) <= n109; 
   BU12_D(8) <= n110; 
   BU12_D(9) <= n111; 
   BU12_D(10) <= n112; 
   BU12_D(11) <= n113; 
   BU12_D(12) <= n114; 
   BU12_D(13) <= n115; 
   BU12_D(14) <= n116; 
   BU12_D(15) <= n117; 
   BU12_D(16) <= n118; 
   BU12_D(17) <= n119; 
   BU12_D(18) <= n120; 
   BU12_D(19) <= n121; 
   BU12_D(20) <= n122; 
   BU12_D(21) <= n123; 
   BU12_D(22) <= n124; 
   BU12_D(23) <= n125; 
   BU12_D(24) <= n126; 
   n216 <= BU12_Q(0); 
   n217 <= BU12_Q(1); 
   n218 <= BU12_Q(2); 
   n219 <= BU12_Q(3); 
   n220 <= BU12_Q(4); 
   n221 <= BU12_Q(5); 
   n222 <= BU12_Q(6); 
   n223 <= BU12_Q(7); 
   n224 <= BU12_Q(8); 
   n225 <= BU12_Q(9); 
   n226 <= BU12_Q(10); 
   n227 <= BU12_Q(11); 
   n228 <= BU12_Q(12); 
   n229 <= BU12_Q(13); 
   n230 <= BU12_Q(14); 
   n231 <= BU12_Q(15); 
   n232 <= BU12_Q(16); 
   n233 <= BU12_Q(17); 
   n234 <= BU12_Q(18); 
   n235 <= BU12_Q(19); 
   n236 <= BU12_Q(20); 
   n237 <= BU12_Q(21); 
   n238 <= BU12_Q(22); 
   n239 <= BU12_Q(23); 
   n240 <= BU12_Q(24); 
   BU12_CLK <= n133; 
   BU12_CE <= n2; 
   BU12 : C_REG_FD_V7_0 
      GENERIC MAP ( 
         c_width => 25, 
         c_has_ce => 1, 
         c_sinit_val => "0000000000000000000000000", 
         c_has_sinit => 0, 
         c_ainit_val => "0000000000000000000000000", 
         c_has_aset => 0, 
         c_sync_enable => 0, 
         c_enable_rlocs => 0, 
         c_has_aclr => 0, 
         c_has_sset => 0, 
         c_sync_priority => 0, 
         c_has_ainit => 0, 
         c_has_sclr => 0 
      ) 
      PORT MAP ( 
         D => BU12_D, 
         Q => BU12_Q, 
         CLK => BU12_CLK, 
         CE => BU12_CE 
      ); 
 
   BU64_A(0) <= n19; 
   BU64_A(1) <= n20; 
   BU64_A(2) <= n21; 
   BU64_A(3) <= n22; 
   BU64_A(4) <= n23; 
   BU64_A(5) <= n24; 
   BU64_A(6) <= n25; 
   BU64_A(7) <= n26; 
   BU64_A(8) <= n27; 
   BU64_A(9) <= n28; 
   BU64_A(10) <= n29; 
   BU64_A(11) <= n30; 
   BU64_A(12) <= n31; 
   BU64_A(13) <= n32; 
   BU64_A(14) <= n33; 
   BU64_A(15) <= n34; 
   BU64_A(16) <= n35; 
   BU64_A(17) <= n36; 
   BU64_A(18) <= n37; 
   BU64_A(19) <= n38; 
   BU64_A(20) <= n39; 
   BU64_A(21) <= n40; 
   BU64_A(22) <= n41; 
   BU64_A(23) <= n42; 
   BU64_A(24) <= n43; 
   BU64_B(0) <= n216; 
   BU64_B(1) <= n217; 
   BU64_B(2) <= n218; 
   BU64_B(3) <= n219; 
   BU64_B(4) <= n220; 
   BU64_B(5) <= n221; 
   BU64_B(6) <= n222; 
   BU64_B(7) <= n223; 
   BU64_B(8) <= n224; 
   BU64_B(9) <= n225; 
   BU64_B(10) <= n226; 
   BU64_B(11) <= n227; 
   BU64_B(12) <= n228; 
   BU64_B(13) <= n229; 
   BU64_B(14) <= n230; 
   BU64_B(15) <= n231; 
   BU64_B(16) <= n232; 
   BU64_B(17) <= n233; 
   BU64_B(18) <= n234; 
   BU64_B(19) <= n235; 
   BU64_B(20) <= n236; 
   BU64_B(21) <= n237; 
   BU64_B(22) <= n238; 
   BU64_B(23) <= n239; 
   BU64_B(24) <= n240; 
   n19 <= BU64_Q(0); 
   n20 <= BU64_Q(1); 
   n21 <= BU64_Q(2); 
   n22 <= BU64_Q(3); 
   n23 <= BU64_Q(4); 
   n24 <= BU64_Q(5); 
   n25 <= BU64_Q(6); 
   n26 <= BU64_Q(7); 
   n27 <= BU64_Q(8); 
   n28 <= BU64_Q(9); 
   n29 <= BU64_Q(10); 
   n30 <= BU64_Q(11); 
   n31 <= BU64_Q(12); 
   n32 <= BU64_Q(13); 
   n33 <= BU64_Q(14); 
   n34 <= BU64_Q(15); 
   n35 <= BU64_Q(16); 
   n36 <= BU64_Q(17); 
   n37 <= BU64_Q(18); 
   n38 <= BU64_Q(19); 
   n39 <= BU64_Q(20); 
   n40 <= BU64_Q(21); 
   n41 <= BU64_Q(22); 
   n42 <= BU64_Q(23); 
   n43 <= BU64_Q(24); 
   BU64_CLK <= n133; 
   BU64_CE <= n134; 
   BU64 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 1, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 1, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 24, 
         c_latency => 1, 
         c_sinit_val => "0000000000000000000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 1, 
         c_has_add => 0, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "0000000000000000000000000", 
         c_add_mode => 0, 
         c_has_aclr => 0, 
         c_out_width => 25, 
         c_low_bit => 0, 
         c_ainit_val => "0000000000000000000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 25, 
         c_a_width => 25, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 0 
      ) 
      PORT MAP ( 
         A => BU64_A, 
         B => BU64_B, 
         Q => BU64_Q, 
         CLK => BU64_CLK, 
         CE => BU64_CE 
      ); 
 
   BU214_CLK <= n133; 
   n44 <= BU214_SDOUT; 
   BU214_CE <= n134; 
   BU214 : C_SHIFT_FD_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_has_d => 0, 
         c_sync_priority => 1, 
         c_has_sclr => 0, 
         c_fill_data => 1, 
         c_width => 1, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_has_sdout => 1, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 0, 
         c_shift_type => 1, 
         c_has_sdin => 0, 
         c_has_lsb_2_msb => 0 
      ) 
      PORT MAP ( 
         CLK => BU214_CLK, 
         SDOUT => BU214_SDOUT, 
         CE => BU214_CE 
      ); 
 
   BU538_A(0) <= n21; 
   BU538_A(1) <= n22; 
   BU538_A(2) <= n23; 
   BU538_A(3) <= n24; 
   BU538_A(4) <= n25; 
   BU538_A(5) <= n26; 
   BU538_A(6) <= n27; 
   BU538_A(7) <= n28; 
   BU538_A(8) <= n29; 
   BU538_A(9) <= n30; 
   BU538_A(10) <= n31; 
   BU538_A(11) <= n32; 
   BU538_A(12) <= n33; 
   BU538_A(13) <= n34; 
   BU538_A(14) <= n35; 
   BU538_A(15) <= n36; 
   BU538_A(16) <= n37; 
   BU538_A(17) <= n38; 
   BU538_A(18) <= n39; 
   BU538_A(19) <= n40; 
   BU538_A(20) <= n41; 
   BU538_A(21) <= n42; 
   BU538_A(22) <= n43; 
   BU538_B(0) <= n59; 
   BU538_B(1) <= n60; 
   BU538_B(2) <= n61; 
   BU538_B(3) <= n62; 
   BU538_B(4) <= n63; 
   BU538_B(5) <= n64; 
   BU538_B(6) <= n65; 
   BU538_B(7) <= n66; 
   BU538_B(8) <= n67; 
   BU538_B(9) <= n68; 
   n45 <= BU538_Q(0); 
   n46 <= BU538_Q(1); 
   n47 <= BU538_Q(2); 
   n48 <= BU538_Q(3); 
   n49 <= BU538_Q(4); 
   n50 <= BU538_Q(5); 
   n51 <= BU538_Q(6); 
   n52 <= BU538_Q(7); 
   n53 <= BU538_Q(8); 
   n54 <= BU538_Q(9); 
   n55 <= BU538_Q(10); 
   n56 <= BU538_Q(11); 
   n57 <= BU538_Q(12); 
   n58 <= BU538_Q(13); 
   BU538_CLK <= n133; 
   BU538_CE <= n134; 
   BU538 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 1, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 1, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 22, 
         c_latency => 1, 
         c_sinit_val => "00000000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 0, 
         c_has_add => 0, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "00000000000000000000000", 
         c_add_mode => 0, 
         c_has_aclr => 0, 
         c_out_width => 14, 
         c_low_bit => 9, 
         c_ainit_val => "00000000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 10, 
         c_a_width => 23, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 0 
      ) 
      PORT MAP ( 
         A => BU538_A, 
         B => BU538_B, 
         Q => BU538_Q, 
         CLK => BU538_CLK, 
         CE => BU538_CE 
      ); 
 
   BU477_A(0) <= n1115; 
   BU477_A(1) <= n1116; 
   BU477_A(2) <= n1117; 
   BU477_A(3) <= n1118; 
   BU477_A(4) <= n1119; 
   BU477_A(5) <= n1120; 
   BU477_A(6) <= n1121; 
   BU477_A(7) <= n1122; 
   BU477_A(8) <= n1123; 
   BU477_B(0) <= n1223; 
   BU477_B(1) <= n1224; 
   BU477_B(2) <= n1225; 
   BU477_B(3) <= n1226; 
   BU477_B(4) <= n1227; 
   BU477_B(5) <= n1228; 
   BU477_B(6) <= n1229; 
   BU477_B(7) <= n1230; 
   BU477_B(8) <= n1231; 
   n59 <= BU477_Q(0); 
   n60 <= BU477_Q(1); 
   n61 <= BU477_Q(2); 
   n62 <= BU477_Q(3); 
   n63 <= BU477_Q(4); 
   n64 <= BU477_Q(5); 
   n65 <= BU477_Q(6); 
   n66 <= BU477_Q(7); 
   n67 <= BU477_Q(8); 
   n68 <= BU477_Q(9); 
   BU477_CLK <= n133; 
   BU477_CE <= n134; 
   BU477 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 0, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 0, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 9, 
         c_latency => 1, 
         c_sinit_val => "0000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 0, 
         c_has_add => 0, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "0000000000", 
         c_add_mode => 0, 
         c_has_aclr => 0, 
         c_out_width => 10, 
         c_low_bit => 0, 
         c_ainit_val => "0000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 9, 
         c_a_width => 9, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 0 
      ) 
      PORT MAP ( 
         A => BU477_A, 
         B => BU477_B, 
         Q => BU477_Q, 
         CLK => BU477_CLK, 
         CE => BU477_CE 
      ); 
 
   BU291_A(0) <= n1014; 
   BU291_A(1) <= n1015; 
   BU291_A(2) <= n1016; 
   BU291_A(3) <= n1017; 
   BU291_A(4) <= n1018; 
   BU291_A(5) <= n1019; 
   BU291_A(6) <= n1020; 
   BU291_A(7) <= n1021; 
   BU291_B(0) <= n1064; 
   BU291_B(1) <= n1065; 
   BU291_B(2) <= n1066; 
   BU291_B(3) <= n1067; 
   BU291_B(4) <= n1068; 
   BU291_B(5) <= n1069; 
   BU291_B(6) <= n1070; 
   BU291_B(7) <= n1071; 
   n1115 <= BU291_Q(0); 
   n1116 <= BU291_Q(1); 
   n1117 <= BU291_Q(2); 
   n1118 <= BU291_Q(3); 
   n1119 <= BU291_Q(4); 
   n1120 <= BU291_Q(5); 
   n1121 <= BU291_Q(6); 
   n1122 <= BU291_Q(7); 
   n1123 <= BU291_Q(8); 
   BU291_CLK <= n133; 
   BU291_CE <= n134; 
   BU291 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 0, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 0, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 8, 
         c_latency => 1, 
         c_sinit_val => "000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 0, 
         c_has_add => 0, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "000000000", 
         c_add_mode => 0, 
         c_has_aclr => 0, 
         c_out_width => 9, 
         c_low_bit => 0, 
         c_ainit_val => "000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 8, 
         c_a_width => 8, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 0 
      ) 
      PORT MAP ( 
         A => BU291_A, 
         B => BU291_B, 
         Q => BU291_Q, 
         CLK => BU291_CLK, 
         CE => BU291_CE 
      ); 
 
   BU222_I(0) <= n1023; 
   BU222_I(1) <= n1024; 
   BU222_I(2) <= n1025; 
   BU222_I(3) <= n1021; 
   BU222_T <= '0'; 
   BU222_EN <= '0'; 
   BU222_CLK <= '0'; 
   BU222_CE <= '0'; 
   BU222_ACLR <= '0'; 
   BU222_ASET <= '0'; 
   BU222_AINIT <= '0'; 
   BU222_SCLR <= '0'; 
   BU222_SSET <= '0'; 
   BU222_SINIT <= '0'; 
   n1022 <= BU222_O; 
   BU222 : C_GATE_BIT_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_gate_type => 4, 
         c_sync_priority => 1, 
         c_has_sclr => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_pipe_stages => 0, 
         c_has_ce => 0, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_has_o => 1, 
         c_inputs => 4, 
         c_input_inv_mask => "0000" 
      ) 
      PORT MAP ( 
         I => BU222_I, 
         T => BU222_T, 
         EN => BU222_EN, 
         Q => BU222_Q, 
         CLK => BU222_CLK, 
         CE => BU222_CE, 
         ACLR => BU222_ACLR, 
         ASET => BU222_ASET, 
         AINIT => BU222_AINIT, 
         SCLR => BU222_SCLR, 
         SSET => BU222_SSET, 
         SINIT => BU222_SINIT, 
         O => BU222_O 
      ); 
 
   BU227_CLK <= n133; 
   BU227_SDIN <= n1022; 
   n1023 <= BU227_Q(0); 
   n1024 <= BU227_Q(2); 
   n1025 <= BU227_Q(3); 
   n1014 <= BU227_Q(5); 
   n1015 <= BU227_Q(6); 
   n1016 <= BU227_Q(7); 
   n1017 <= BU227_Q(8); 
   n1018 <= BU227_Q(9); 
   n1019 <= BU227_Q(10); 
   n1020 <= BU227_Q(11); 
   n1021 <= BU227_Q(12); 
   BU227_CE <= n134; 
   BU227 : C_SHIFT_FD_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_has_d => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_fill_data => 5, 
         c_width => 13, 
         c_enable_rlocs => 0, 
         c_ainit_val => "1000000000000", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_has_sdout => 0, 
         c_sinit_val => "1000000000000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_shift_type => 0, 
         c_has_sdin => 1, 
         c_has_lsb_2_msb => 0 
      ) 
      PORT MAP ( 
         CLK => BU227_CLK, 
         SDIN => BU227_SDIN, 
         Q => BU227_Q, 
         CE => BU227_CE 
      ); 
 
   BU256_I(0) <= n1073; 
   BU256_I(1) <= n1074; 
   BU256_I(2) <= n1067; 
   BU256_I(3) <= n1071; 
   BU256_T <= '0'; 
   BU256_EN <= '0'; 
   BU256_CLK <= '0'; 
   BU256_CE <= '0'; 
   BU256_ACLR <= '0'; 
   BU256_ASET <= '0'; 
   BU256_AINIT <= '0'; 
   BU256_SCLR <= '0'; 
   BU256_SSET <= '0'; 
   BU256_SINIT <= '0'; 
   n1072 <= BU256_O; 
   BU256 : C_GATE_BIT_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_gate_type => 4, 
         c_sync_priority => 1, 
         c_has_sclr => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_pipe_stages => 0, 
         c_has_ce => 0, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_has_o => 1, 
         c_inputs => 4, 
         c_input_inv_mask => "0000" 
      ) 
      PORT MAP ( 
         I => BU256_I, 
         T => BU256_T, 
         EN => BU256_EN, 
         Q => BU256_Q, 
         CLK => BU256_CLK, 
         CE => BU256_CE, 
         ACLR => BU256_ACLR, 
         ASET => BU256_ASET, 
         AINIT => BU256_AINIT, 
         SCLR => BU256_SCLR, 
         SSET => BU256_SSET, 
         SINIT => BU256_SINIT, 
         O => BU256_O 
      ); 
 
   BU261_CLK <= n133; 
   BU261_SDIN <= n1072; 
   n1073 <= BU261_Q(0); 
   n1074 <= BU261_Q(5); 
   n1064 <= BU261_Q(6); 
   n1065 <= BU261_Q(7); 
   n1066 <= BU261_Q(8); 
   n1067 <= BU261_Q(9); 
   n1068 <= BU261_Q(10); 
   n1069 <= BU261_Q(11); 
   n1070 <= BU261_Q(12); 
   n1071 <= BU261_Q(13); 
   BU261_CE <= n134; 
   BU261 : C_SHIFT_FD_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_has_d => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_fill_data => 5, 
         c_width => 14, 
         c_enable_rlocs => 0, 
         c_ainit_val => "10000000000000", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_has_sdout => 0, 
         c_sinit_val => "10000000000000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_shift_type => 0, 
         c_has_sdin => 1, 
         c_has_lsb_2_msb => 0 
      ) 
      PORT MAP ( 
         CLK => BU261_CLK, 
         SDIN => BU261_SDIN, 
         Q => BU261_Q, 
         CE => BU261_CE 
      ); 
 
   BU423_A(0) <= n1124; 
   BU423_A(1) <= n1125; 
   BU423_A(2) <= n1126; 
   BU423_A(3) <= n1127; 
   BU423_A(4) <= n1128; 
   BU423_A(5) <= n1129; 
   BU423_A(6) <= n1130; 
   BU423_A(7) <= n1131; 
   BU423_B(0) <= n1170; 
   BU423_B(1) <= n1171; 
   BU423_B(2) <= n1172; 
   BU423_B(3) <= n1173; 
   BU423_B(4) <= n1174; 
   BU423_B(5) <= n1175; 
   BU423_B(6) <= n1176; 
   BU423_B(7) <= n1177; 
   n1223 <= BU423_Q(0); 
   n1224 <= BU423_Q(1); 
   n1225 <= BU423_Q(2); 
   n1226 <= BU423_Q(3); 
   n1227 <= BU423_Q(4); 
   n1228 <= BU423_Q(5); 
   n1229 <= BU423_Q(6); 
   n1230 <= BU423_Q(7); 
   n1231 <= BU423_Q(8); 
   BU423_CLK <= n133; 
   BU423_CE <= n134; 
   BU423 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 0, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 0, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 8, 
         c_latency => 1, 
         c_sinit_val => "000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 0, 
         c_has_add => 0, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "000000000", 
         c_add_mode => 0, 
         c_has_aclr => 0, 
         c_out_width => 9, 
         c_low_bit => 0, 
         c_ainit_val => "000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 8, 
         c_a_width => 8, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 0 
      ) 
      PORT MAP ( 
         A => BU423_A, 
         B => BU423_B, 
         Q => BU423_Q, 
         CLK => BU423_CLK, 
         CE => BU423_CE 
      ); 
 
   BU346_I(0) <= n1133; 
   BU346_I(1) <= n1131; 
   BU346_T <= '0'; 
   BU346_EN <= '0'; 
   BU346_CLK <= '0'; 
   BU346_CE <= '0'; 
   BU346_ACLR <= '0'; 
   BU346_ASET <= '0'; 
   BU346_AINIT <= '0'; 
   BU346_SCLR <= '0'; 
   BU346_SSET <= '0'; 
   BU346_SINIT <= '0'; 
   n1132 <= BU346_O; 
   BU346 : C_GATE_BIT_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_gate_type => 4, 
         c_sync_priority => 1, 
         c_has_sclr => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_pipe_stages => 0, 
         c_has_ce => 0, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_has_o => 1, 
         c_inputs => 2, 
         c_input_inv_mask => "00" 
      ) 
      PORT MAP ( 
         I => BU346_I, 
         T => BU346_T, 
         EN => BU346_EN, 
         Q => BU346_Q, 
         CLK => BU346_CLK, 
         CE => BU346_CE, 
         ACLR => BU346_ACLR, 
         ASET => BU346_ASET, 
         AINIT => BU346_AINIT, 
         SCLR => BU346_SCLR, 
         SSET => BU346_SSET, 
         SINIT => BU346_SINIT, 
         O => BU346_O 
      ); 
 
   BU351_CLK <= n133; 
   BU351_SDIN <= n1132; 
   n1133 <= BU351_Q(0); 
   n1124 <= BU351_Q(7); 
   n1125 <= BU351_Q(8); 
   n1126 <= BU351_Q(9); 
   n1127 <= BU351_Q(10); 
   n1128 <= BU351_Q(11); 
   n1129 <= BU351_Q(12); 
   n1130 <= BU351_Q(13); 
   n1131 <= BU351_Q(14); 
   BU351_CE <= n134; 
   BU351 : C_SHIFT_FD_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_has_d => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_fill_data => 5, 
         c_width => 15, 
         c_enable_rlocs => 0, 
         c_ainit_val => "100000000000000", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_has_sdout => 0, 
         c_sinit_val => "100000000000000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_shift_type => 0, 
         c_has_sdin => 1, 
         c_has_lsb_2_msb => 0 
      ) 
      PORT MAP ( 
         CLK => BU351_CLK, 
         SDIN => BU351_SDIN, 
         Q => BU351_Q, 
         CE => BU351_CE 
      ); 
 
   BU384_I(0) <= n1179; 
   BU384_I(1) <= n1180; 
   BU384_I(2) <= n1173; 
   BU384_I(3) <= n1177; 
   BU384_T <= '0'; 
   BU384_EN <= '0'; 
   BU384_CLK <= '0'; 
   BU384_CE <= '0'; 
   BU384_ACLR <= '0'; 
   BU384_ASET <= '0'; 
   BU384_AINIT <= '0'; 
   BU384_SCLR <= '0'; 
   BU384_SSET <= '0'; 
   BU384_SINIT <= '0'; 
   n1178 <= BU384_O; 
   BU384 : C_GATE_BIT_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_gate_type => 4, 
         c_sync_priority => 1, 
         c_has_sclr => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_pipe_stages => 0, 
         c_has_ce => 0, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_has_o => 1, 
         c_inputs => 4, 
         c_input_inv_mask => "0000" 
      ) 
      PORT MAP ( 
         I => BU384_I, 
         T => BU384_T, 
         EN => BU384_EN, 
         Q => BU384_Q, 
         CLK => BU384_CLK, 
         CE => BU384_CE, 
         ACLR => BU384_ACLR, 
         ASET => BU384_ASET, 
         AINIT => BU384_AINIT, 
         SCLR => BU384_SCLR, 
         SSET => BU384_SSET, 
         SINIT => BU384_SINIT, 
         O => BU384_O 
      ); 
 
   BU389_CLK <= n133; 
   BU389_SDIN <= n1178; 
   n1179 <= BU389_Q(0); 
   n1180 <= BU389_Q(2); 
   n1170 <= BU389_Q(8); 
   n1171 <= BU389_Q(9); 
   n1172 <= BU389_Q(10); 
   n1173 <= BU389_Q(11); 
   n1174 <= BU389_Q(12); 
   n1175 <= BU389_Q(13); 
   n1176 <= BU389_Q(14); 
   n1177 <= BU389_Q(15); 
   BU389_CE <= n134; 
   BU389 : C_SHIFT_FD_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_has_d => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_fill_data => 5, 
         c_width => 16, 
         c_enable_rlocs => 0, 
         c_ainit_val => "1000000000000000", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_has_sdout => 0, 
         c_sinit_val => "1000000000000000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 1, 
         c_shift_type => 0, 
         c_has_sdin => 1, 
         c_has_lsb_2_msb => 0 
      ) 
      PORT MAP ( 
         CLK => BU389_CLK, 
         SDIN => BU389_SDIN, 
         Q => BU389_Q, 
         CE => BU389_CE 
      ); 
 
   BU742_D(0) <= n45; 
   BU742_D(1) <= n46; 
   BU742_D(2) <= n47; 
   BU742_D(3) <= n48; 
   BU742_D(4) <= n49; 
   BU742_D(5) <= n50; 
   BU742_D(6) <= n51; 
   BU742_D(7) <= n52; 
   BU742_D(8) <= n53; 
   BU742_D(9) <= n54; 
   BU742_D(10) <= n55; 
   BU742_D(11) <= n56; 
   BU742_D(12) <= n57; 
   BU742_D(13) <= n58; 
   n1867 <= BU742_Q(0); 
   n1868 <= BU742_Q(1); 
   n1869 <= BU742_Q(2); 
   n1870 <= BU742_Q(3); 
   n1871 <= BU742_Q(4); 
   n1872 <= BU742_Q(5); 
   n1873 <= BU742_Q(6); 
   n1874 <= BU742_Q(7); 
   n1875 <= BU742_Q(8); 
   n1876 <= BU742_Q(9); 
   n1877 <= BU742_Q(10); 
   n1878 <= BU742_Q(11); 
   n1879 <= BU742_Q(12); 
   n1880 <= BU742_Q(13); 
   BU742_CLK <= n133; 
   BU742_CE <= n134; 
   BU742 : C_REG_FD_V7_0 
      GENERIC MAP ( 
         c_width => 14, 
         c_has_ce => 1, 
         c_sinit_val => "00000000000000", 
         c_has_sinit => 0, 
         c_ainit_val => "00000000000000", 
         c_has_aset => 0, 
         c_sync_enable => 0, 
         c_enable_rlocs => 0, 
         c_has_aclr => 0, 
         c_has_sset => 0, 
         c_sync_priority => 0, 
         c_has_ainit => 0, 
         c_has_sclr => 0 
      ) 
      PORT MAP ( 
         D => BU742_D, 
         Q => BU742_Q, 
         CLK => BU742_CLK, 
         CE => BU742_CE 
      ); 
 
   BU773_A(0) <= n1867; 
   BU773_A(1) <= n1868; 
   BU773_A(2) <= n1869; 
   BU773_A(3) <= n1870; 
   BU773_A(4) <= n1871; 
   BU773_A(5) <= n1872; 
   BU773_A(6) <= n1873; 
   BU773_A(7) <= n1874; 
   BU773_A(8) <= n1875; 
   BU773_A(9) <= n1876; 
   BU773_A(10) <= n1877; 
   BU773_A(11) <= n1878; 
   BU773_BYPASS <= n1879; 
   BU773_CLK <= n133; 
   n1907 <= BU773_Q(0); 
   n1908 <= BU773_Q(1); 
   n1909 <= BU773_Q(2); 
   n1910 <= BU773_Q(3); 
   n1911 <= BU773_Q(4); 
   n1912 <= BU773_Q(5); 
   n1913 <= BU773_Q(6); 
   n1914 <= BU773_Q(7); 
   n1915 <= BU773_Q(8); 
   n1916 <= BU773_Q(9); 
   n1917 <= BU773_Q(10); 
   n1918 <= BU773_Q(11); 
   BU773_CE <= n134; 
   BU773 : C_TWOS_COMP_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_width => 12, 
         c_enable_rlocs => 0, 
         c_has_bypass => 1, 
         c_ainit_val => "0000000000000", 
         c_bypass_low => 1, 
         c_pipe_stages => 0, 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0000000000000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_s => 0, 
         c_bypass_enable => 1, 
         c_has_q => 1 
      ) 
      PORT MAP ( 
         A => BU773_A, 
         BYPASS => BU773_BYPASS, 
         CLK => BU773_CLK, 
         Q => BU773_Q, 
         CE => BU773_CE 
      ); 
 
   BU866_CLK <= n133; 
   BU866_D(0) <= n1880; 
   n1881 <= BU866_Q(0); 
   BU866_CE <= n134; 
   BU866 : C_SHIFT_RAM_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_read_mif => 0, 
         c_has_a => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_width => 1, 
         c_enable_rlocs => 0, 
         c_default_data_radix => 2, 
         c_generate_mif => 0, 
         c_ainit_val => "0", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_mem_init_radix => 2, 
         c_sync_enable => 0, 
         c_depth => 2, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_shift_type => 0, 
         c_mem_init_file => "null", 
         c_default_data => "0", 
         c_reg_last_bit => 1, 
         c_addr_width => 1 
      ) 
      PORT MAP ( 
         CLK => BU866_CLK, 
         D => BU866_D, 
         Q => BU866_Q, 
         CE => BU866_CE 
      ); 
 
   BU874_CLK <= n133; 
   BU874_D(0) <= n1879; 
   n1882 <= BU874_Q(0); 
   BU874_CE <= n134; 
   BU874 : C_SHIFT_RAM_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_read_mif => 0, 
         c_has_a => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_width => 1, 
         c_enable_rlocs => 0, 
         c_default_data_radix => 2, 
         c_generate_mif => 0, 
         c_ainit_val => "0", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_mem_init_radix => 2, 
         c_sync_enable => 0, 
         c_depth => 2, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_shift_type => 0, 
         c_mem_init_file => "null", 
         c_default_data => "0", 
         c_reg_last_bit => 1, 
         c_addr_width => 1 
      ) 
      PORT MAP ( 
         CLK => BU874_CLK, 
         D => BU874_D, 
         Q => BU874_Q, 
         CE => BU874_CE 
      ); 
 
   BU885_I0 <= n1881; 
   BU885_I1 <= n1882; 
   BU885_I2 <= n1923; 
   BU885_I3 <= '0'; 
   n2340 <= BU885_O; 
   BU885 : LUT4 
      GENERIC MAP ( 
         INIT  => X"9595" 
      ) 
      PORT MAP ( 
         I0 => BU885_I0, 
         I1 => BU885_I1, 
         I2 => BU885_I2, 
         I3 => BU885_I3, 
         O => BU885_O 
      ); 
 
   BU886_D <= n2340; 
   BU886_C <= n133; 
   BU886_CE <= n134; 
   BU886_PRE <= '0'; 
   n1925 <= BU886_Q; 
   BU886 : FDPE 
      PORT MAP ( 
         D => BU886_D, 
         C => BU886_C, 
         CE => BU886_CE, 
         PRE => BU886_PRE, 
         Q => BU886_Q 
      ); 
 
   BU890_I0 <= n1881; 
   BU890_I1 <= n1882; 
   BU890_I2 <= n1923; 
   BU890_I3 <= n1924; 
   n2359 <= BU890_O; 
   BU890 : LUT4 
      GENERIC MAP ( 
         INIT  => X"002a" 
      ) 
      PORT MAP ( 
         I0 => BU890_I0, 
         I1 => BU890_I1, 
         I2 => BU890_I2, 
         I3 => BU890_I3, 
         O => BU890_O 
      ); 
 
   BU891_D <= n2359; 
   BU891_C <= n133; 
   BU891_CE <= n134; 
   n1926 <= BU891_Q; 
   BU891 : FDE 
      PORT MAP ( 
         D => BU891_D, 
         C => BU891_C, 
         CE => BU891_CE, 
         Q => BU891_Q 
      ); 
 
   BU895_I0 <= '0'; 
   BU895_I1 <= n1882; 
   BU895_I2 <= n1923; 
   BU895_I3 <= '0'; 
   n2377 <= BU895_O; 
   BU895 : LUT4 
      GENERIC MAP ( 
         INIT  => X"c0c0" 
      ) 
      PORT MAP ( 
         I0 => BU895_I0, 
         I1 => BU895_I1, 
         I2 => BU895_I2, 
         I3 => BU895_I3, 
         O => BU895_O 
      ); 
 
   BU896_D <= n2377; 
   BU896_C <= n133; 
   BU896_CE <= n134; 
   n1922 <= BU896_Q; 
   BU896 : FDE 
      PORT MAP ( 
         D => BU896_D, 
         C => BU896_C, 
         CE => BU896_CE, 
         Q => BU896_Q 
      ); 
 
   BU898_A(0) <= n1907; 
   BU898_A(1) <= n1908; 
   BU898_A(2) <= n1909; 
   BU898_A(3) <= n1910; 
   BU898_A(4) <= n1911; 
   BU898_A(5) <= n1912; 
   BU898_A(6) <= n1913; 
   BU898_A(7) <= n1914; 
   BU898_A(8) <= n1915; 
   BU898_A(9) <= n1916; 
   BU898_A(10) <= n1917; 
   BU898_A(11) <= n1918; 
   BU898_CLK <= n133; 
   BU898_CE <= n134; 
   BU898_ACLR <= '0'; 
   n1924 <= BU898_QA_GE_B; 
   BU898 : C_COMPARE_V7_0 
      GENERIC MAP ( 
         c_has_qa_ge_b => 1, 
         c_has_aset => 0, 
         c_has_qa_ne_b => 0, 
         c_has_qa_lt_b => 0, 
         c_has_a_gt_b => 0, 
         c_has_a_eq_b => 0, 
         c_data_type => 1, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_has_qa_gt_b => 0, 
         c_width => 12, 
         c_has_qa_eq_b => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_has_a_le_b => 0, 
         c_has_ce => 1, 
         c_pipe_stages => 0, 
         c_has_aclr => 1, 
         c_sync_enable => 0, 
         c_has_sset => 0, 
         c_has_qa_le_b => 0, 
         c_b_constant => 1, 
         c_has_a_ge_b => 0, 
         c_has_a_ne_b => 0, 
         c_has_a_lt_b => 0, 
         c_b_value => "111111110010" 
      ) 
      PORT MAP ( 
         A => BU898_A, 
         CLK => BU898_CLK, 
         CE => BU898_CE, 
         ACLR => BU898_ACLR, 
         QA_GE_B => BU898_QA_GE_B 
      ); 
 
   BU940_A(0) <= n1907; 
   BU940_A(1) <= n1908; 
   BU940_A(2) <= n1909; 
   BU940_A(3) <= n1910; 
   BU940_A(4) <= n1911; 
   BU940_A(5) <= n1912; 
   BU940_A(6) <= n1913; 
   BU940_A(7) <= n1914; 
   BU940_A(8) <= n1915; 
   BU940_A(9) <= n1916; 
   BU940_A(10) <= n1917; 
   BU940_A(11) <= n1918; 
   BU940_CLK <= n133; 
   BU940_CE <= n134; 
   BU940_ACLR <= '0'; 
   n1923 <= BU940_QA_EQ_B; 
   BU940 : C_COMPARE_V7_0 
      GENERIC MAP ( 
         c_has_qa_ge_b => 0, 
         c_has_aset => 0, 
         c_has_qa_ne_b => 0, 
         c_has_qa_lt_b => 0, 
         c_has_a_gt_b => 0, 
         c_has_a_eq_b => 0, 
         c_data_type => 1, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_has_qa_gt_b => 0, 
         c_width => 12, 
         c_has_qa_eq_b => 1, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_has_a_le_b => 0, 
         c_has_ce => 1, 
         c_pipe_stages => 0, 
         c_has_aclr => 1, 
         c_sync_enable => 0, 
         c_has_sset => 0, 
         c_has_qa_le_b => 0, 
         c_b_constant => 1, 
         c_has_a_ge_b => 0, 
         c_has_a_ne_b => 0, 
         c_has_a_lt_b => 0, 
         c_b_value => "000000000000" 
      ) 
      PORT MAP ( 
         A => BU940_A, 
         CLK => BU940_CLK, 
         CE => BU940_CE, 
         ACLR => BU940_ACLR, 
         QA_EQ_B => BU940_QA_EQ_B 
      ); 
 
   BU959_D(0) <= n45; 
   BU959_D(1) <= n46; 
   BU959_D(2) <= n47; 
   BU959_D(3) <= n48; 
   BU959_D(4) <= n49; 
   BU959_D(5) <= n50; 
   BU959_D(6) <= n51; 
   BU959_D(7) <= n52; 
   BU959_D(8) <= n53; 
   BU959_D(9) <= n54; 
   BU959_D(10) <= n55; 
   BU959_D(11) <= n56; 
   BU959_D(12) <= n57; 
   BU959_D(13) <= n58; 
   n1958 <= BU959_Q(0); 
   n1959 <= BU959_Q(1); 
   n1960 <= BU959_Q(2); 
   n1961 <= BU959_Q(3); 
   n1962 <= BU959_Q(4); 
   n1963 <= BU959_Q(5); 
   n1964 <= BU959_Q(6); 
   n1965 <= BU959_Q(7); 
   n1966 <= BU959_Q(8); 
   n1967 <= BU959_Q(9); 
   n1968 <= BU959_Q(10); 
   n1969 <= BU959_Q(11); 
   n1970 <= BU959_Q(12); 
   n1971 <= BU959_Q(13); 
   BU959_CLK <= n133; 
   BU959_CE <= n134; 
   BU959 : C_REG_FD_V7_0 
      GENERIC MAP ( 
         c_width => 14, 
         c_has_ce => 1, 
         c_sinit_val => "00000000000000", 
         c_has_sinit => 0, 
         c_ainit_val => "00000000000000", 
         c_has_aset => 0, 
         c_sync_enable => 0, 
         c_enable_rlocs => 0, 
         c_has_aclr => 0, 
         c_has_sset => 0, 
         c_sync_priority => 0, 
         c_has_ainit => 0, 
         c_has_sclr => 0 
      ) 
      PORT MAP ( 
         D => BU959_D, 
         Q => BU959_Q, 
         CLK => BU959_CLK, 
         CE => BU959_CE 
      ); 
 
   BU990_A(0) <= n1958; 
   BU990_A(1) <= n1959; 
   BU990_A(2) <= n1960; 
   BU990_A(3) <= n1961; 
   BU990_A(4) <= n1962; 
   BU990_A(5) <= n1963; 
   BU990_A(6) <= n1964; 
   BU990_A(7) <= n1965; 
   BU990_A(8) <= n1966; 
   BU990_A(9) <= n1967; 
   BU990_A(10) <= n1968; 
   BU990_A(11) <= n1969; 
   BU990_BYPASS <= n1970; 
   BU990_CLK <= n133; 
   n1998 <= BU990_Q(0); 
   n1999 <= BU990_Q(1); 
   n2000 <= BU990_Q(2); 
   n2001 <= BU990_Q(3); 
   n2002 <= BU990_Q(4); 
   n2003 <= BU990_Q(5); 
   n2004 <= BU990_Q(6); 
   n2005 <= BU990_Q(7); 
   n2006 <= BU990_Q(8); 
   n2007 <= BU990_Q(9); 
   n2008 <= BU990_Q(10); 
   n2009 <= BU990_Q(11); 
   BU990_CE <= n134; 
   BU990 : C_TWOS_COMP_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_width => 12, 
         c_enable_rlocs => 0, 
         c_has_bypass => 1, 
         c_ainit_val => "0000000000000", 
         c_bypass_low => 0, 
         c_pipe_stages => 0, 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_sinit_val => "0000000000000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_s => 0, 
         c_bypass_enable => 1, 
         c_has_q => 1 
      ) 
      PORT MAP ( 
         A => BU990_A, 
         BYPASS => BU990_BYPASS, 
         CLK => BU990_CLK, 
         Q => BU990_Q, 
         CE => BU990_CE 
      ); 
 
   BU1085_CLK <= n133; 
   BU1085_D(0) <= n1971; 
   n1972 <= BU1085_Q(0); 
   BU1085_CE <= n134; 
   BU1085 : C_SHIFT_RAM_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_read_mif => 0, 
         c_has_a => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_width => 1, 
         c_enable_rlocs => 0, 
         c_default_data_radix => 2, 
         c_generate_mif => 0, 
         c_ainit_val => "0", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_mem_init_radix => 2, 
         c_sync_enable => 0, 
         c_depth => 2, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_shift_type => 0, 
         c_mem_init_file => "null", 
         c_default_data => "0", 
         c_reg_last_bit => 1, 
         c_addr_width => 1 
      ) 
      PORT MAP ( 
         CLK => BU1085_CLK, 
         D => BU1085_D, 
         Q => BU1085_Q, 
         CE => BU1085_CE 
      ); 
 
   BU1093_CLK <= n133; 
   BU1093_D(0) <= n1970; 
   n1973 <= BU1093_Q(0); 
   BU1093_CE <= n134; 
   BU1093 : C_SHIFT_RAM_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_read_mif => 0, 
         c_has_a => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_width => 1, 
         c_enable_rlocs => 0, 
         c_default_data_radix => 2, 
         c_generate_mif => 0, 
         c_ainit_val => "0", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_mem_init_radix => 2, 
         c_sync_enable => 0, 
         c_depth => 2, 
         c_has_ainit => 0, 
         c_sinit_val => "0", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_shift_type => 0, 
         c_mem_init_file => "null", 
         c_default_data => "0", 
         c_reg_last_bit => 1, 
         c_addr_width => 1 
      ) 
      PORT MAP ( 
         CLK => BU1093_CLK, 
         D => BU1093_D, 
         Q => BU1093_Q, 
         CE => BU1093_CE 
      ); 
 
   BU1104_I0 <= n1972; 
   BU1104_I1 <= n1973; 
   BU1104_I2 <= n2014; 
   BU1104_I3 <= '0'; 
   n2659 <= BU1104_O; 
   BU1104 : LUT4 
      GENERIC MAP ( 
         INIT  => X"a9a9" 
      ) 
      PORT MAP ( 
         I0 => BU1104_I0, 
         I1 => BU1104_I1, 
         I2 => BU1104_I2, 
         I3 => BU1104_I3, 
         O => BU1104_O 
      ); 
 
   BU1105_D <= n2659; 
   BU1105_C <= n133; 
   BU1105_CE <= n134; 
   BU1105_PRE <= '0'; 
   n2016 <= BU1105_Q; 
   BU1105 : FDPE 
      PORT MAP ( 
         D => BU1105_D, 
         C => BU1105_C, 
         CE => BU1105_CE, 
         PRE => BU1105_PRE, 
         Q => BU1105_Q 
      ); 
 
   BU1109_I0 <= n1972; 
   BU1109_I1 <= n1973; 
   BU1109_I2 <= n2014; 
   BU1109_I3 <= n2015; 
   n2678 <= BU1109_O; 
   BU1109 : LUT4 
      GENERIC MAP ( 
         INIT  => X"0046" 
      ) 
      PORT MAP ( 
         I0 => BU1109_I0, 
         I1 => BU1109_I1, 
         I2 => BU1109_I2, 
         I3 => BU1109_I3, 
         O => BU1109_O 
      ); 
 
   BU1110_D <= n2678; 
   BU1110_C <= n133; 
   BU1110_CE <= n134; 
   n2017 <= BU1110_Q; 
   BU1110 : FDE 
      PORT MAP ( 
         D => BU1110_D, 
         C => BU1110_C, 
         CE => BU1110_CE, 
         Q => BU1110_Q 
      ); 
 
   BU1114_I0 <= '0'; 
   BU1114_I1 <= n1973; 
   BU1114_I2 <= n2014; 
   BU1114_I3 <= '0'; 
   n2696 <= BU1114_O; 
   BU1114 : LUT4 
      GENERIC MAP ( 
         INIT  => X"3030" 
      ) 
      PORT MAP ( 
         I0 => BU1114_I0, 
         I1 => BU1114_I1, 
         I2 => BU1114_I2, 
         I3 => BU1114_I3, 
         O => BU1114_O 
      ); 
 
   BU1115_D <= n2696; 
   BU1115_C <= n133; 
   BU1115_CE <= n134; 
   n2013 <= BU1115_Q; 
   BU1115 : FDE 
      PORT MAP ( 
         D => BU1115_D, 
         C => BU1115_C, 
         CE => BU1115_CE, 
         Q => BU1115_Q 
      ); 
 
   BU1117_A(0) <= n1998; 
   BU1117_A(1) <= n1999; 
   BU1117_A(2) <= n2000; 
   BU1117_A(3) <= n2001; 
   BU1117_A(4) <= n2002; 
   BU1117_A(5) <= n2003; 
   BU1117_A(6) <= n2004; 
   BU1117_A(7) <= n2005; 
   BU1117_A(8) <= n2006; 
   BU1117_A(9) <= n2007; 
   BU1117_A(10) <= n2008; 
   BU1117_A(11) <= n2009; 
   BU1117_CLK <= n133; 
   BU1117_CE <= n134; 
   BU1117_ACLR <= '0'; 
   n2015 <= BU1117_QA_GE_B; 
   BU1117 : C_COMPARE_V7_0 
      GENERIC MAP ( 
         c_has_qa_ge_b => 1, 
         c_has_aset => 0, 
         c_has_qa_ne_b => 0, 
         c_has_qa_lt_b => 0, 
         c_has_a_gt_b => 0, 
         c_has_a_eq_b => 0, 
         c_data_type => 1, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_has_qa_gt_b => 0, 
         c_width => 12, 
         c_has_qa_eq_b => 0, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_has_a_le_b => 0, 
         c_has_ce => 1, 
         c_pipe_stages => 0, 
         c_has_aclr => 1, 
         c_sync_enable => 0, 
         c_has_sset => 0, 
         c_has_qa_le_b => 0, 
         c_b_constant => 1, 
         c_has_a_ge_b => 0, 
         c_has_a_ne_b => 0, 
         c_has_a_lt_b => 0, 
         c_b_value => "111111110010" 
      ) 
      PORT MAP ( 
         A => BU1117_A, 
         CLK => BU1117_CLK, 
         CE => BU1117_CE, 
         ACLR => BU1117_ACLR, 
         QA_GE_B => BU1117_QA_GE_B 
      ); 
 
   BU1159_A(0) <= n1998; 
   BU1159_A(1) <= n1999; 
   BU1159_A(2) <= n2000; 
   BU1159_A(3) <= n2001; 
   BU1159_A(4) <= n2002; 
   BU1159_A(5) <= n2003; 
   BU1159_A(6) <= n2004; 
   BU1159_A(7) <= n2005; 
   BU1159_A(8) <= n2006; 
   BU1159_A(9) <= n2007; 
   BU1159_A(10) <= n2008; 
   BU1159_A(11) <= n2009; 
   BU1159_CLK <= n133; 
   BU1159_CE <= n134; 
   BU1159_ACLR <= '0'; 
   n2014 <= BU1159_QA_EQ_B; 
   BU1159 : C_COMPARE_V7_0 
      GENERIC MAP ( 
         c_has_qa_ge_b => 0, 
         c_has_aset => 0, 
         c_has_qa_ne_b => 0, 
         c_has_qa_lt_b => 0, 
         c_has_a_gt_b => 0, 
         c_has_a_eq_b => 0, 
         c_data_type => 1, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_has_qa_gt_b => 0, 
         c_width => 12, 
         c_has_qa_eq_b => 1, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0", 
         c_has_a_le_b => 0, 
         c_has_ce => 1, 
         c_pipe_stages => 0, 
         c_has_aclr => 1, 
         c_sync_enable => 0, 
         c_has_sset => 0, 
         c_has_qa_le_b => 0, 
         c_b_constant => 1, 
         c_has_a_ge_b => 0, 
         c_has_a_ne_b => 0, 
         c_has_a_lt_b => 0, 
         c_b_value => "000000000000" 
      ) 
      PORT MAP ( 
         A => BU1159_A, 
         CLK => BU1159_CLK, 
         CE => BU1159_CE, 
         ACLR => BU1159_ACLR, 
         QA_EQ_B => BU1159_QA_EQ_B 
      ); 
 
   BU652_addra(11) <= n1918; 
   BU652_addra(10) <= n1917; 
   BU652_addra(9) <= n1916; 
   BU652_addra(8) <= n1915; 
   BU652_addra(7) <= n1914; 
   BU652_addra(6) <= n1913; 
   BU652_addra(5) <= n1912; 
   BU652_addra(4) <= n1911; 
   BU652_addra(3) <= n1910; 
   BU652_addra(2) <= n1909; 
   BU652_addra(1) <= n1908; 
   BU652_addra(0) <= n1907; 
   BU652_addrb(11) <= n2009; 
   BU652_addrb(10) <= n2008; 
   BU652_addrb(9) <= n2007; 
   BU652_addrb(8) <= n2006; 
   BU652_addrb(7) <= n2005; 
   BU652_addrb(6) <= n2004; 
   BU652_addrb(5) <= n2003; 
   BU652_addrb(4) <= n2002; 
   BU652_addrb(3) <= n2001; 
   BU652_addrb(2) <= n2000; 
   BU652_addrb(1) <= n1999; 
   BU652_addrb(0) <= n1998; 
   BU652_clka <= n133; 
   BU652_clkb <= n133; 
   BU652_dina(14) <= '0'; 
   BU652_dina(13) <= '0'; 
   BU652_dina(12) <= '0'; 
   BU652_dina(11) <= '0'; 
   BU652_dina(10) <= '0'; 
   BU652_dina(9) <= '0'; 
   BU652_dina(8) <= '0'; 
   BU652_dina(7) <= '0'; 
   BU652_dina(6) <= '0'; 
   BU652_dina(5) <= '0'; 
   BU652_dina(4) <= '0'; 
   BU652_dina(3) <= '0'; 
   BU652_dina(2) <= '0'; 
   BU652_dina(1) <= '0'; 
   BU652_dina(0) <= '0'; 
   BU652_dinb(14) <= '0'; 
   BU652_dinb(13) <= '0'; 
   BU652_dinb(12) <= '0'; 
   BU652_dinb(11) <= '0'; 
   BU652_dinb(10) <= '0'; 
   BU652_dinb(9) <= '0'; 
   BU652_dinb(8) <= '0'; 
   BU652_dinb(7) <= '0'; 
   BU652_dinb(6) <= '0'; 
   BU652_dinb(5) <= '0'; 
   BU652_dinb(4) <= '0'; 
   BU652_dinb(3) <= '0'; 
   BU652_dinb(2) <= '0'; 
   BU652_dinb(1) <= '0'; 
   BU652_dinb(0) <= '0'; 
   n1941 <= BU652_douta(14); 
   n1940 <= BU652_douta(13); 
   n1939 <= BU652_douta(12); 
   n1938 <= BU652_douta(11); 
   n1937 <= BU652_douta(10); 
   n1936 <= BU652_douta(9); 
   n1935 <= BU652_douta(8); 
   n1934 <= BU652_douta(7); 
   n1933 <= BU652_douta(6); 
   n1932 <= BU652_douta(5); 
   n1931 <= BU652_douta(4); 
   n1930 <= BU652_douta(3); 
   n1929 <= BU652_douta(2); 
   n1928 <= BU652_douta(1); 
   n1927 <= BU652_douta(0); 
   n2032 <= BU652_doutb(14); 
   n2031 <= BU652_doutb(13); 
   n2030 <= BU652_doutb(12); 
   n2029 <= BU652_doutb(11); 
   n2028 <= BU652_doutb(10); 
   n2027 <= BU652_doutb(9); 
   n2026 <= BU652_doutb(8); 
   n2025 <= BU652_doutb(7); 
   n2024 <= BU652_doutb(6); 
   n2023 <= BU652_doutb(5); 
   n2022 <= BU652_doutb(4); 
   n2021 <= BU652_doutb(3); 
   n2020 <= BU652_doutb(2); 
   n2019 <= BU652_doutb(1); 
   n2018 <= BU652_doutb(0); 
   BU652_ena <= n134; 
   BU652_enb <= n134; 
   BU652_nda <= '0'; 
   BU652_ndb <= '0'; 
   BU652_sinita <= '0'; 
   BU652_sinitb <= '0'; 
   BU652_wea <= '0'; 
   BU652_web <= '0'; 
   BU652 : blkmemdp_v6_0 
      GENERIC MAP ( 
         c_reg_inputsb => 0, 
         c_reg_inputsa => 0, 
         c_has_ndb => 0, 
         c_has_nda => 0, 
         c_ytop_addr => "1024", 
         c_has_rfdb => 0, 
         c_has_rfda => 0, 
         c_ywea_is_high => 1, 
         c_yena_is_high => 1, 
         c_yhierarchy => "hierarchy1", 
         c_yclka_is_rising => 1, 
         c_ysinita_is_high => 1, 
         c_ybottom_addr => "0", 
         c_width_b => 15, 
         c_width_a => 15, 
         c_sinita_value => "0000", 
         c_sinitb_value => "0000", 
         c_limit_data_pitch => 18, 
         c_write_modeb => 0, 
         c_write_modea => 0, 
         c_has_rdyb => 0, 
         c_yuse_single_primitive => 0, 
         c_has_rdya => 0, 
         c_addra_width => 12, 
         c_addrb_width => 12, 
         c_has_limit_data_pitch => 0, 
         c_default_data => "0000", 
         c_pipe_stages_b => 1, 
         c_yweb_is_high => 1, 
         c_yenb_is_high => 1, 
         c_pipe_stages_a => 1, 
         c_yclkb_is_rising => 1, 
         c_yydisable_warnings => 1, 
         c_enable_rlocs => 0, 
         c_ysinitb_is_high => 1, 
         c_has_web => 0, 
         c_has_default_data => 0, 
         c_has_wea => 0, 
         c_has_sinitb => 0, 
         c_has_sinita => 0, 
         c_has_dinb => 0, 
         c_has_dina => 0, 
         c_ymake_bmm => 0, 
         c_has_enb => 1, 
         c_has_ena => 1, 
         c_mem_init_file => "ddsqam_SINCOS_TABLE_TRIG_ROM.mif", 
         c_depth_b => 4096, 
         c_depth_a => 4096, 
         c_has_doutb => 1, 
         c_has_douta => 1, 
         c_yprimitive_type => "4kx4" 
      ) 
      PORT MAP ( 
         addra => BU652_addra, 
         addrb => BU652_addrb, 
         clka => BU652_clka, 
         clkb => BU652_clkb, 
         dina => BU652_dina, 
         dinb => BU652_dinb, 
         douta => BU652_douta, 
         doutb => BU652_doutb, 
         ena => BU652_ena, 
         enb => BU652_enb, 
         nda => BU652_nda, 
         ndb => BU652_ndb, 
         rfda => BU652_rfda, 
         rfdb => BU652_rfdb, 
         rdya => BU652_rdya, 
         rdyb => BU652_rdyb, 
         sinita => BU652_sinita, 
         sinitb => BU652_sinitb, 
         wea => BU652_wea, 
         web => BU652_web 
      ); 
 
   BU1178_A(0) <= '0'; 
   BU1178_A(1) <= '0'; 
   BU1178_A(2) <= '0'; 
   BU1178_A(3) <= '0'; 
   BU1178_A(4) <= '0'; 
   BU1178_A(5) <= '0'; 
   BU1178_A(6) <= '0'; 
   BU1178_A(7) <= '0'; 
   BU1178_A(8) <= '0'; 
   BU1178_A(9) <= '0'; 
   BU1178_A(10) <= '0'; 
   BU1178_A(11) <= '0'; 
   BU1178_A(12) <= '0'; 
   BU1178_A(13) <= '0'; 
   BU1178_A(14) <= '0'; 
   BU1178_A(15) <= '0'; 
   BU1178_B(0) <= n1927; 
   BU1178_B(1) <= n1928; 
   BU1178_B(2) <= n1929; 
   BU1178_B(3) <= n1930; 
   BU1178_B(4) <= n1931; 
   BU1178_B(5) <= n1932; 
   BU1178_B(6) <= n1933; 
   BU1178_B(7) <= n1934; 
   BU1178_B(8) <= n1935; 
   BU1178_B(9) <= n1936; 
   BU1178_B(10) <= n1937; 
   BU1178_B(11) <= n1938; 
   BU1178_B(12) <= n1939; 
   BU1178_B(13) <= n1940; 
   BU1178_B(14) <= n1941; 
   BU1178_B(15) <= n1922; 
   BU1178_C_IN <= n1926; 
   BU1178_ADD <= n1925; 
   n135 <= BU1178_Q(0); 
   n136 <= BU1178_Q(1); 
   n137 <= BU1178_Q(2); 
   n138 <= BU1178_Q(3); 
   n139 <= BU1178_Q(4); 
   n140 <= BU1178_Q(5); 
   n141 <= BU1178_Q(6); 
   n142 <= BU1178_Q(7); 
   n143 <= BU1178_Q(8); 
   n144 <= BU1178_Q(9); 
   n145 <= BU1178_Q(10); 
   n146 <= BU1178_Q(11); 
   n147 <= BU1178_Q(12); 
   n148 <= BU1178_Q(13); 
   n149 <= BU1178_Q(14); 
   n150 <= BU1178_Q(15); 
   BU1178_CLK <= n133; 
   BU1178_CE <= n2049; 
   BU1178 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 1, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 1, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 15, 
         c_latency => 1, 
         c_sinit_val => "0000000000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 1, 
         c_has_add => 1, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "0000000000000000", 
         c_add_mode => 2, 
         c_has_aclr => 0, 
         c_out_width => 16, 
         c_low_bit => 0, 
         c_ainit_val => "0000000000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 16, 
         c_a_width => 16, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 1 
      ) 
      PORT MAP ( 
         A => BU1178_A, 
         B => BU1178_B, 
         C_IN => BU1178_C_IN, 
         ADD => BU1178_ADD, 
         Q => BU1178_Q, 
         CLK => BU1178_CLK, 
         CE => BU1178_CE 
      ); 
 
   BU1275_CLK <= n133; 
   BU1275_SDIN <= n44; 
   n2067 <= BU1275_SDOUT; 
   BU1275_CE <= n134; 
   BU1275 : C_SHIFT_FD_V7_0 
      GENERIC MAP ( 
         c_has_aset => 0, 
         c_has_d => 0, 
         c_sync_priority => 0, 
         c_has_sclr => 0, 
         c_fill_data => 5, 
         c_width => 4, 
         c_enable_rlocs => 0, 
         c_ainit_val => "0000", 
         c_has_ce => 1, 
         c_has_aclr => 0, 
         c_sync_enable => 0, 
         c_has_ainit => 0, 
         c_has_sdout => 1, 
         c_sinit_val => "0000", 
         c_has_sset => 0, 
         c_has_sinit => 0, 
         c_has_q => 0, 
         c_shift_type => 1, 
         c_has_sdin => 1, 
         c_has_lsb_2_msb => 0 
      ) 
      PORT MAP ( 
         CLK => BU1275_CLK, 
         SDIN => BU1275_SDIN, 
         SDOUT => BU1275_SDOUT, 
         CE => BU1275_CE 
      ); 
 
   BU1287_I0 <= n134; 
   BU1287_I1 <= n2067; 
   BU1287_I2 <= '0'; 
   BU1287_I3 <= '0'; 
   n2049 <= BU1287_O; 
   BU1287 : LUT4 
      GENERIC MAP ( 
         INIT  => X"8888" 
      ) 
      PORT MAP ( 
         I0 => BU1287_I0, 
         I1 => BU1287_I1, 
         I2 => BU1287_I2, 
         I3 => BU1287_I3, 
         O => BU1287_O 
      ); 
 
   BU1290_A(0) <= '0'; 
   BU1290_A(1) <= '0'; 
   BU1290_A(2) <= '0'; 
   BU1290_A(3) <= '0'; 
   BU1290_A(4) <= '0'; 
   BU1290_A(5) <= '0'; 
   BU1290_A(6) <= '0'; 
   BU1290_A(7) <= '0'; 
   BU1290_A(8) <= '0'; 
   BU1290_A(9) <= '0'; 
   BU1290_A(10) <= '0'; 
   BU1290_A(11) <= '0'; 
   BU1290_A(12) <= '0'; 
   BU1290_A(13) <= '0'; 
   BU1290_A(14) <= '0'; 
   BU1290_A(15) <= '0'; 
   BU1290_B(0) <= n2018; 
   BU1290_B(1) <= n2019; 
   BU1290_B(2) <= n2020; 
   BU1290_B(3) <= n2021; 
   BU1290_B(4) <= n2022; 
   BU1290_B(5) <= n2023; 
   BU1290_B(6) <= n2024; 
   BU1290_B(7) <= n2025; 
   BU1290_B(8) <= n2026; 
   BU1290_B(9) <= n2027; 
   BU1290_B(10) <= n2028; 
   BU1290_B(11) <= n2029; 
   BU1290_B(12) <= n2030; 
   BU1290_B(13) <= n2031; 
   BU1290_B(14) <= n2032; 
   BU1290_B(15) <= n2013; 
   BU1290_C_IN <= n2017; 
   BU1290_ADD <= n2016; 
   n151 <= BU1290_Q(0); 
   n152 <= BU1290_Q(1); 
   n153 <= BU1290_Q(2); 
   n154 <= BU1290_Q(3); 
   n155 <= BU1290_Q(4); 
   n156 <= BU1290_Q(5); 
   n157 <= BU1290_Q(6); 
   n158 <= BU1290_Q(7); 
   n159 <= BU1290_Q(8); 
   n160 <= BU1290_Q(9); 
   n161 <= BU1290_Q(10); 
   n162 <= BU1290_Q(11); 
   n163 <= BU1290_Q(12); 
   n164 <= BU1290_Q(13); 
   n165 <= BU1290_Q(14); 
   n166 <= BU1290_Q(15); 
   BU1290_CLK <= n133; 
   BU1290_CE <= n2049; 
   BU1290 : C_ADDSUB_V7_0 
      GENERIC MAP ( 
         c_has_bypass_with_cin => 0, 
         c_a_type => 1, 
         c_has_sclr => 0, 
         c_has_aset => 0, 
         c_has_b_out => 0, 
         c_sync_priority => 0, 
         c_has_s => 1, 
         c_has_q => 1, 
         c_bypass_enable => 1, 
         c_b_constant => 0, 
         c_has_ovfl => 0, 
         c_high_bit => 15, 
         c_latency => 1, 
         c_sinit_val => "0000000000000000", 
         c_has_bypass => 0, 
         c_pipe_stages => 0, 
         c_has_sset => 0, 
         c_has_ainit => 0, 
         c_has_a_signed => 0, 
         c_has_q_c_out => 0, 
         c_b_type => 1, 
         c_has_add => 1, 
         c_has_sinit => 0, 
         c_has_b_in => 0, 
         c_has_b_signed => 0, 
         c_bypass_low => 0, 
         c_enable_rlocs => 0, 
         c_b_value => "0000000000000000", 
         c_add_mode => 2, 
         c_has_aclr => 0, 
         c_out_width => 16, 
         c_low_bit => 0, 
         c_ainit_val => "0000000000000000", 
         c_has_q_ovfl => 0, 
         c_has_q_b_out => 0, 
         c_has_c_out => 0, 
         c_b_width => 16, 
         c_a_width => 16, 
         c_sync_enable => 0, 
         c_has_ce => 1, 
         c_has_c_in => 1 
      ) 
      PORT MAP ( 
         A => BU1290_A, 
         B => BU1290_B, 
         C_IN => BU1290_C_IN, 
         ADD => BU1290_ADD, 
         Q => BU1290_Q, 
         CLK => BU1290_CLK, 
         CE => BU1290_CE 
      ); 
 
 
END xilinx; 
 
 
-- synthesis translate_on