www.pudn.com > 16QAM_verilog.rar > ddsqam.v, change:2011-07-13,size:84743b


/******************************************************************************* 
*     This file is owned and controlled by Xilinx and must be used             * 
*     solely for design, simulation, implementation and creation of            * 
*     design files limited to Xilinx devices or technologies. Use              * 
*     with non-Xilinx devices or technologies is expressly prohibited          * 
*     and immediately terminates your license.                                 * 
*                                                                              * 
*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            * 
*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  * 
*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          * 
*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              * 
*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                * 
*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  * 
*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         * 
*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 * 
*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  * 
*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           * 
*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          * 
*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          * 
*     FOR A PARTICULAR PURPOSE.                                                * 
*                                                                              * 
*     Xilinx products are not intended for use in life support                 * 
*     appliances, devices, or systems. Use in such applications are            * 
*     expressly prohibited.                                                    * 
*                                                                              * 
*     (c) Copyright 1995-2007 Xilinx, Inc.                                     * 
*     All rights reserved.                                                     * 
*******************************************************************************/ 
 
/* Behavioural components instantiated: 
C_COMPARE_V7_0 
C_SHIFT_RAM_V7_0 
C_REG_FD_V7_0 
BLKMEMDP_V6_0 
C_TWOS_COMP_V7_0 
C_GATE_BIT_V7_0 
C_SHIFT_FD_V7_0 
C_ADDSUB_V7_0 
*/ 
 
`timescale 1ns/1ps 
 
module ddsqam( 
   DATA, 
   WE, 
   A, 
   CLK, 
   CE, 
   SINE, 
   COSINE 
   ); // synthesis black_box 
 
   input [24 : 0] DATA; 
   input WE; 
   input [4 : 0] A; 
   input CLK; 
   input CE; 
   output [15 : 0] SINE; 
   output [15 : 0] COSINE; 
//synthesis translate_off 
   wire n0 = 1'b0; 
   wire n1 = 1'b1; 
   wire n2; 
   wire n3; 
   wire n4; 
   wire n5; 
   wire n6; 
   wire n7; 
   wire n8; 
   wire n19; 
   wire n20; 
   wire n21; 
   wire n22; 
   wire n23; 
   wire n24; 
   wire n25; 
   wire n26; 
   wire n27; 
   wire n28; 
   wire n29; 
   wire n30; 
   wire n31; 
   wire n32; 
   wire n33; 
   wire n34; 
   wire n35; 
   wire n36; 
   wire n37; 
   wire n38; 
   wire n39; 
   wire n40; 
   wire n41; 
   wire n42; 
   wire n43; 
   wire n44; 
   wire n45; 
   wire n46; 
   wire n47; 
   wire n48; 
   wire n49; 
   wire n50; 
   wire n51; 
   wire n52; 
   wire n53; 
   wire n54; 
   wire n55; 
   wire n56; 
   wire n57; 
   wire n58; 
   wire n59; 
   wire n60; 
   wire n61; 
   wire n62; 
   wire n63; 
   wire n64; 
   wire n65; 
   wire n66; 
   wire n67; 
   wire n68; 
   wire n102; 
   wire n103; 
   wire n104; 
   wire n105; 
   wire n106; 
   wire n107; 
   wire n108; 
   wire n109; 
   wire n110; 
   wire n111; 
   wire n112; 
   wire n113; 
   wire n114; 
   wire n115; 
   wire n116; 
   wire n117; 
   wire n118; 
   wire n119; 
   wire n120; 
   wire n121; 
   wire n122; 
   wire n123; 
   wire n124; 
   wire n125; 
   wire n126; 
   wire n133; 
   wire n134; 
   wire n135; 
   wire n136; 
   wire n137; 
   wire n138; 
   wire n139; 
   wire n140; 
   wire n141; 
   wire n142; 
   wire n143; 
   wire n144; 
   wire n145; 
   wire n146; 
   wire n147; 
   wire n148; 
   wire n149; 
   wire n150; 
   wire n151; 
   wire n152; 
   wire n153; 
   wire n154; 
   wire n155; 
   wire n156; 
   wire n157; 
   wire n158; 
   wire n159; 
   wire n160; 
   wire n161; 
   wire n162; 
   wire n163; 
   wire n164; 
   wire n165; 
   wire n166; 
   wire n216; 
   wire n217; 
   wire n218; 
   wire n219; 
   wire n220; 
   wire n221; 
   wire n222; 
   wire n223; 
   wire n224; 
   wire n225; 
   wire n226; 
   wire n227; 
   wire n228; 
   wire n229; 
   wire n230; 
   wire n231; 
   wire n232; 
   wire n233; 
   wire n234; 
   wire n235; 
   wire n236; 
   wire n237; 
   wire n238; 
   wire n239; 
   wire n240; 
   wire n1014; 
   wire n1015; 
   wire n1016; 
   wire n1017; 
   wire n1018; 
   wire n1019; 
   wire n1020; 
   wire n1021; 
   wire n1022; 
   wire n1023; 
   wire n1024; 
   wire n1025; 
   wire n1064; 
   wire n1065; 
   wire n1066; 
   wire n1067; 
   wire n1068; 
   wire n1069; 
   wire n1070; 
   wire n1071; 
   wire n1072; 
   wire n1073; 
   wire n1074; 
   wire n1115; 
   wire n1116; 
   wire n1117; 
   wire n1118; 
   wire n1119; 
   wire n1120; 
   wire n1121; 
   wire n1122; 
   wire n1123; 
   wire n1124; 
   wire n1125; 
   wire n1126; 
   wire n1127; 
   wire n1128; 
   wire n1129; 
   wire n1130; 
   wire n1131; 
   wire n1132; 
   wire n1133; 
   wire n1170; 
   wire n1171; 
   wire n1172; 
   wire n1173; 
   wire n1174; 
   wire n1175; 
   wire n1176; 
   wire n1177; 
   wire n1178; 
   wire n1179; 
   wire n1180; 
   wire n1223; 
   wire n1224; 
   wire n1225; 
   wire n1226; 
   wire n1227; 
   wire n1228; 
   wire n1229; 
   wire n1230; 
   wire n1231; 
   wire n1867; 
   wire n1868; 
   wire n1869; 
   wire n1870; 
   wire n1871; 
   wire n1872; 
   wire n1873; 
   wire n1874; 
   wire n1875; 
   wire n1876; 
   wire n1877; 
   wire n1878; 
   wire n1879; 
   wire n1880; 
   wire n1881; 
   wire n1882; 
   wire n1907; 
   wire n1908; 
   wire n1909; 
   wire n1910; 
   wire n1911; 
   wire n1912; 
   wire n1913; 
   wire n1914; 
   wire n1915; 
   wire n1916; 
   wire n1917; 
   wire n1918; 
   wire n1922; 
   wire n1923; 
   wire n1924; 
   wire n1925; 
   wire n1926; 
   wire n1927; 
   wire n1928; 
   wire n1929; 
   wire n1930; 
   wire n1931; 
   wire n1932; 
   wire n1933; 
   wire n1934; 
   wire n1935; 
   wire n1936; 
   wire n1937; 
   wire n1938; 
   wire n1939; 
   wire n1940; 
   wire n1941; 
   wire n1958; 
   wire n1959; 
   wire n1960; 
   wire n1961; 
   wire n1962; 
   wire n1963; 
   wire n1964; 
   wire n1965; 
   wire n1966; 
   wire n1967; 
   wire n1968; 
   wire n1969; 
   wire n1970; 
   wire n1971; 
   wire n1972; 
   wire n1973; 
   wire n1998; 
   wire n1999; 
   wire n2000; 
   wire n2001; 
   wire n2002; 
   wire n2003; 
   wire n2004; 
   wire n2005; 
   wire n2006; 
   wire n2007; 
   wire n2008; 
   wire n2009; 
   wire n2013; 
   wire n2014; 
   wire n2015; 
   wire n2016; 
   wire n2017; 
   wire n2018; 
   wire n2019; 
   wire n2020; 
   wire n2021; 
   wire n2022; 
   wire n2023; 
   wire n2024; 
   wire n2025; 
   wire n2026; 
   wire n2027; 
   wire n2028; 
   wire n2029; 
   wire n2030; 
   wire n2031; 
   wire n2032; 
   wire n2049; 
   wire n2067; 
   wire n2340; 
   wire n2359; 
   wire n2377; 
   wire n2659; 
   wire n2678; 
   wire n2696; 
   assign n102 = DATA[0]; 
   assign n103 = DATA[1]; 
   assign n104 = DATA[2]; 
   assign n105 = DATA[3]; 
   assign n106 = DATA[4]; 
   assign n107 = DATA[5]; 
   assign n108 = DATA[6]; 
   assign n109 = DATA[7]; 
   assign n110 = DATA[8]; 
   assign n111 = DATA[9]; 
   assign n112 = DATA[10]; 
   assign n113 = DATA[11]; 
   assign n114 = DATA[12]; 
   assign n115 = DATA[13]; 
   assign n116 = DATA[14]; 
   assign n117 = DATA[15]; 
   assign n118 = DATA[16]; 
   assign n119 = DATA[17]; 
   assign n120 = DATA[18]; 
   assign n121 = DATA[19]; 
   assign n122 = DATA[20]; 
   assign n123 = DATA[21]; 
   assign n124 = DATA[22]; 
   assign n125 = DATA[23]; 
   assign n126 = DATA[24]; 
   assign n8 = WE; 
   assign n3 = A[0]; 
   assign n4 = A[1]; 
   assign n5 = A[2]; 
   assign n6 = A[3]; 
   assign n7 = A[4]; 
   assign n133 = CLK; 
   assign n134 = CE; 
   assign SINE[0] = n135; 
   assign SINE[1] = n136; 
   assign SINE[2] = n137; 
   assign SINE[3] = n138; 
   assign SINE[4] = n139; 
   assign SINE[5] = n140; 
   assign SINE[6] = n141; 
   assign SINE[7] = n142; 
   assign SINE[8] = n143; 
   assign SINE[9] = n144; 
   assign SINE[10] = n145; 
   assign SINE[11] = n146; 
   assign SINE[12] = n147; 
   assign SINE[13] = n148; 
   assign SINE[14] = n149; 
   assign SINE[15] = n150; 
   assign COSINE[0] = n151; 
   assign COSINE[1] = n152; 
   assign COSINE[2] = n153; 
   assign COSINE[3] = n154; 
   assign COSINE[4] = n155; 
   assign COSINE[5] = n156; 
   assign COSINE[6] = n157; 
   assign COSINE[7] = n158; 
   assign COSINE[8] = n159; 
   assign COSINE[9] = n160; 
   assign COSINE[10] = n161; 
   assign COSINE[11] = n162; 
   assign COSINE[12] = n163; 
   assign COSINE[13] = n164; 
   assign COSINE[14] = n165; 
   assign COSINE[15] = n166; 
 
      wire [5 : 0] BU2_I; 
         assign BU2_I[0] = n3; 
         assign BU2_I[1] = n4; 
         assign BU2_I[2] = n5; 
         assign BU2_I[3] = n6; 
         assign BU2_I[4] = n7; 
         assign BU2_I[5] = n8; 
      wire BU2_T; 
         assign BU2_T = 1'b0; 
      wire BU2_EN; 
         assign BU2_EN = 1'b0; 
      wire BU2_Q; 
      wire BU2_CLK; 
         assign BU2_CLK = 1'b0; 
      wire BU2_CE; 
         assign BU2_CE = 1'b0; 
      wire BU2_ACLR; 
         assign BU2_ACLR = 1'b0; 
      wire BU2_ASET; 
         assign BU2_ASET = 1'b0; 
      wire BU2_AINIT; 
         assign BU2_AINIT = 1'b0; 
      wire BU2_SCLR; 
         assign BU2_SCLR = 1'b0; 
      wire BU2_SSET; 
         assign BU2_SSET = 1'b0; 
      wire BU2_SINIT; 
         assign BU2_SINIT = 1'b0; 
      wire BU2_O; 
         assign n2 = BU2_O; 
      C_GATE_BIT_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_gate_type*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_ce*/, 
         1    /* c_has_o*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         6    /* c_inputs*/, 
         "011111"    /* c_input_inv_mask*/, 
         0    /* c_pipe_stages*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         1    /* c_sync_priority*/ 
      ) 
      BU2( 
         .I(BU2_I), 
         .T(BU2_T), 
         .EN(BU2_EN), 
         .Q(BU2_Q), 
         .CLK(BU2_CLK), 
         .CE(BU2_CE), 
         .ACLR(BU2_ACLR), 
         .ASET(BU2_ASET), 
         .AINIT(BU2_AINIT), 
         .SCLR(BU2_SCLR), 
         .SSET(BU2_SSET), 
         .SINIT(BU2_SINIT), 
         .O(BU2_O) 
      ); 
 
      wire [24 : 0] BU12_D; 
         assign BU12_D[0] = n102; 
         assign BU12_D[1] = n103; 
         assign BU12_D[2] = n104; 
         assign BU12_D[3] = n105; 
         assign BU12_D[4] = n106; 
         assign BU12_D[5] = n107; 
         assign BU12_D[6] = n108; 
         assign BU12_D[7] = n109; 
         assign BU12_D[8] = n110; 
         assign BU12_D[9] = n111; 
         assign BU12_D[10] = n112; 
         assign BU12_D[11] = n113; 
         assign BU12_D[12] = n114; 
         assign BU12_D[13] = n115; 
         assign BU12_D[14] = n116; 
         assign BU12_D[15] = n117; 
         assign BU12_D[16] = n118; 
         assign BU12_D[17] = n119; 
         assign BU12_D[18] = n120; 
         assign BU12_D[19] = n121; 
         assign BU12_D[20] = n122; 
         assign BU12_D[21] = n123; 
         assign BU12_D[22] = n124; 
         assign BU12_D[23] = n125; 
         assign BU12_D[24] = n126; 
      wire [24 : 0] BU12_Q; 
         assign n216 = BU12_Q[0]; 
         assign n217 = BU12_Q[1]; 
         assign n218 = BU12_Q[2]; 
         assign n219 = BU12_Q[3]; 
         assign n220 = BU12_Q[4]; 
         assign n221 = BU12_Q[5]; 
         assign n222 = BU12_Q[6]; 
         assign n223 = BU12_Q[7]; 
         assign n224 = BU12_Q[8]; 
         assign n225 = BU12_Q[9]; 
         assign n226 = BU12_Q[10]; 
         assign n227 = BU12_Q[11]; 
         assign n228 = BU12_Q[12]; 
         assign n229 = BU12_Q[13]; 
         assign n230 = BU12_Q[14]; 
         assign n231 = BU12_Q[15]; 
         assign n232 = BU12_Q[16]; 
         assign n233 = BU12_Q[17]; 
         assign n234 = BU12_Q[18]; 
         assign n235 = BU12_Q[19]; 
         assign n236 = BU12_Q[20]; 
         assign n237 = BU12_Q[21]; 
         assign n238 = BU12_Q[22]; 
         assign n239 = BU12_Q[23]; 
         assign n240 = BU12_Q[24]; 
      wire BU12_CLK; 
         assign BU12_CLK = n133; 
      wire BU12_CE; 
         assign BU12_CE = n2; 
      C_REG_FD_V7_0 #( 
         "0000000000000000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "0000000000000000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         25    /* c_width*/ 
      ) 
      BU12( 
         .D(BU12_D), 
         .Q(BU12_Q), 
         .CLK(BU12_CLK), 
         .CE(BU12_CE) 
      ); 
 
      wire [24 : 0] BU64_A; 
         assign BU64_A[0] = n19; 
         assign BU64_A[1] = n20; 
         assign BU64_A[2] = n21; 
         assign BU64_A[3] = n22; 
         assign BU64_A[4] = n23; 
         assign BU64_A[5] = n24; 
         assign BU64_A[6] = n25; 
         assign BU64_A[7] = n26; 
         assign BU64_A[8] = n27; 
         assign BU64_A[9] = n28; 
         assign BU64_A[10] = n29; 
         assign BU64_A[11] = n30; 
         assign BU64_A[12] = n31; 
         assign BU64_A[13] = n32; 
         assign BU64_A[14] = n33; 
         assign BU64_A[15] = n34; 
         assign BU64_A[16] = n35; 
         assign BU64_A[17] = n36; 
         assign BU64_A[18] = n37; 
         assign BU64_A[19] = n38; 
         assign BU64_A[20] = n39; 
         assign BU64_A[21] = n40; 
         assign BU64_A[22] = n41; 
         assign BU64_A[23] = n42; 
         assign BU64_A[24] = n43; 
      wire [24 : 0] BU64_B; 
         assign BU64_B[0] = n216; 
         assign BU64_B[1] = n217; 
         assign BU64_B[2] = n218; 
         assign BU64_B[3] = n219; 
         assign BU64_B[4] = n220; 
         assign BU64_B[5] = n221; 
         assign BU64_B[6] = n222; 
         assign BU64_B[7] = n223; 
         assign BU64_B[8] = n224; 
         assign BU64_B[9] = n225; 
         assign BU64_B[10] = n226; 
         assign BU64_B[11] = n227; 
         assign BU64_B[12] = n228; 
         assign BU64_B[13] = n229; 
         assign BU64_B[14] = n230; 
         assign BU64_B[15] = n231; 
         assign BU64_B[16] = n232; 
         assign BU64_B[17] = n233; 
         assign BU64_B[18] = n234; 
         assign BU64_B[19] = n235; 
         assign BU64_B[20] = n236; 
         assign BU64_B[21] = n237; 
         assign BU64_B[22] = n238; 
         assign BU64_B[23] = n239; 
         assign BU64_B[24] = n240; 
      wire [24 : 0] BU64_Q; 
         assign n19 = BU64_Q[0]; 
         assign n20 = BU64_Q[1]; 
         assign n21 = BU64_Q[2]; 
         assign n22 = BU64_Q[3]; 
         assign n23 = BU64_Q[4]; 
         assign n24 = BU64_Q[5]; 
         assign n25 = BU64_Q[6]; 
         assign n26 = BU64_Q[7]; 
         assign n27 = BU64_Q[8]; 
         assign n28 = BU64_Q[9]; 
         assign n29 = BU64_Q[10]; 
         assign n30 = BU64_Q[11]; 
         assign n31 = BU64_Q[12]; 
         assign n32 = BU64_Q[13]; 
         assign n33 = BU64_Q[14]; 
         assign n34 = BU64_Q[15]; 
         assign n35 = BU64_Q[16]; 
         assign n36 = BU64_Q[17]; 
         assign n37 = BU64_Q[18]; 
         assign n38 = BU64_Q[19]; 
         assign n39 = BU64_Q[20]; 
         assign n40 = BU64_Q[21]; 
         assign n41 = BU64_Q[22]; 
         assign n42 = BU64_Q[23]; 
         assign n43 = BU64_Q[24]; 
      wire BU64_CLK; 
         assign BU64_CLK = n133; 
      wire BU64_CE; 
         assign BU64_CE = n134; 
      C_ADDSUB_V7_0 #( 
         0    /* c_add_mode*/, 
         "0000000000000000000000000"    /* c_ainit_val*/, 
         1    /* c_a_type*/, 
         25    /* c_a_width*/, 
         1    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         1    /* c_b_type*/, 
         "0000000000000000000000000"    /* c_b_value*/, 
         25    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         24    /* c_high_bit*/, 
         1    /* c_latency*/, 
         0    /* c_low_bit*/, 
         25    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "0000000000000000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU64( 
         .A(BU64_A), 
         .B(BU64_B), 
         .Q(BU64_Q), 
         .CLK(BU64_CLK), 
         .CE(BU64_CE) 
      ); 
 
      wire BU214_CLK; 
         assign BU214_CLK = n133; 
      wire BU214_SDOUT; 
         assign n44 = BU214_SDOUT; 
      wire BU214_CE; 
         assign BU214_CE = n134; 
      C_SHIFT_FD_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         1    /* c_fill_data*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_d*/, 
         0    /* c_has_lsb_2_msb*/, 
         0    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sdin*/, 
         1    /* c_has_sdout*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         1    /* c_shift_type*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         1    /* c_sync_priority*/, 
         1    /* c_width*/ 
      ) 
      BU214( 
         .CLK(BU214_CLK), 
         .SDOUT(BU214_SDOUT), 
         .CE(BU214_CE) 
      ); 
 
      wire [22 : 0] BU538_A; 
         assign BU538_A[0] = n21; 
         assign BU538_A[1] = n22; 
         assign BU538_A[2] = n23; 
         assign BU538_A[3] = n24; 
         assign BU538_A[4] = n25; 
         assign BU538_A[5] = n26; 
         assign BU538_A[6] = n27; 
         assign BU538_A[7] = n28; 
         assign BU538_A[8] = n29; 
         assign BU538_A[9] = n30; 
         assign BU538_A[10] = n31; 
         assign BU538_A[11] = n32; 
         assign BU538_A[12] = n33; 
         assign BU538_A[13] = n34; 
         assign BU538_A[14] = n35; 
         assign BU538_A[15] = n36; 
         assign BU538_A[16] = n37; 
         assign BU538_A[17] = n38; 
         assign BU538_A[18] = n39; 
         assign BU538_A[19] = n40; 
         assign BU538_A[20] = n41; 
         assign BU538_A[21] = n42; 
         assign BU538_A[22] = n43; 
      wire [9 : 0] BU538_B; 
         assign BU538_B[0] = n59; 
         assign BU538_B[1] = n60; 
         assign BU538_B[2] = n61; 
         assign BU538_B[3] = n62; 
         assign BU538_B[4] = n63; 
         assign BU538_B[5] = n64; 
         assign BU538_B[6] = n65; 
         assign BU538_B[7] = n66; 
         assign BU538_B[8] = n67; 
         assign BU538_B[9] = n68; 
      wire [13 : 0] BU538_Q; 
         assign n45 = BU538_Q[0]; 
         assign n46 = BU538_Q[1]; 
         assign n47 = BU538_Q[2]; 
         assign n48 = BU538_Q[3]; 
         assign n49 = BU538_Q[4]; 
         assign n50 = BU538_Q[5]; 
         assign n51 = BU538_Q[6]; 
         assign n52 = BU538_Q[7]; 
         assign n53 = BU538_Q[8]; 
         assign n54 = BU538_Q[9]; 
         assign n55 = BU538_Q[10]; 
         assign n56 = BU538_Q[11]; 
         assign n57 = BU538_Q[12]; 
         assign n58 = BU538_Q[13]; 
      wire BU538_CLK; 
         assign BU538_CLK = n133; 
      wire BU538_CE; 
         assign BU538_CE = n134; 
      C_ADDSUB_V7_0 #( 
         0    /* c_add_mode*/, 
         "00000000000000"    /* c_ainit_val*/, 
         1    /* c_a_type*/, 
         23    /* c_a_width*/, 
         1    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         0    /* c_b_type*/, 
         "00000000000000000000000"    /* c_b_value*/, 
         10    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         22    /* c_high_bit*/, 
         1    /* c_latency*/, 
         9    /* c_low_bit*/, 
         14    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "00000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU538( 
         .A(BU538_A), 
         .B(BU538_B), 
         .Q(BU538_Q), 
         .CLK(BU538_CLK), 
         .CE(BU538_CE) 
      ); 
 
      wire [8 : 0] BU477_A; 
         assign BU477_A[0] = n1115; 
         assign BU477_A[1] = n1116; 
         assign BU477_A[2] = n1117; 
         assign BU477_A[3] = n1118; 
         assign BU477_A[4] = n1119; 
         assign BU477_A[5] = n1120; 
         assign BU477_A[6] = n1121; 
         assign BU477_A[7] = n1122; 
         assign BU477_A[8] = n1123; 
      wire [8 : 0] BU477_B; 
         assign BU477_B[0] = n1223; 
         assign BU477_B[1] = n1224; 
         assign BU477_B[2] = n1225; 
         assign BU477_B[3] = n1226; 
         assign BU477_B[4] = n1227; 
         assign BU477_B[5] = n1228; 
         assign BU477_B[6] = n1229; 
         assign BU477_B[7] = n1230; 
         assign BU477_B[8] = n1231; 
      wire [9 : 0] BU477_Q; 
         assign n59 = BU477_Q[0]; 
         assign n60 = BU477_Q[1]; 
         assign n61 = BU477_Q[2]; 
         assign n62 = BU477_Q[3]; 
         assign n63 = BU477_Q[4]; 
         assign n64 = BU477_Q[5]; 
         assign n65 = BU477_Q[6]; 
         assign n66 = BU477_Q[7]; 
         assign n67 = BU477_Q[8]; 
         assign n68 = BU477_Q[9]; 
      wire BU477_CLK; 
         assign BU477_CLK = n133; 
      wire BU477_CE; 
         assign BU477_CE = n134; 
      C_ADDSUB_V7_0 #( 
         0    /* c_add_mode*/, 
         "0000000000"    /* c_ainit_val*/, 
         0    /* c_a_type*/, 
         9    /* c_a_width*/, 
         0    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         0    /* c_b_type*/, 
         "0000000000"    /* c_b_value*/, 
         9    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         9    /* c_high_bit*/, 
         1    /* c_latency*/, 
         0    /* c_low_bit*/, 
         10    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "0000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU477( 
         .A(BU477_A), 
         .B(BU477_B), 
         .Q(BU477_Q), 
         .CLK(BU477_CLK), 
         .CE(BU477_CE) 
      ); 
 
      wire [7 : 0] BU291_A; 
         assign BU291_A[0] = n1014; 
         assign BU291_A[1] = n1015; 
         assign BU291_A[2] = n1016; 
         assign BU291_A[3] = n1017; 
         assign BU291_A[4] = n1018; 
         assign BU291_A[5] = n1019; 
         assign BU291_A[6] = n1020; 
         assign BU291_A[7] = n1021; 
      wire [7 : 0] BU291_B; 
         assign BU291_B[0] = n1064; 
         assign BU291_B[1] = n1065; 
         assign BU291_B[2] = n1066; 
         assign BU291_B[3] = n1067; 
         assign BU291_B[4] = n1068; 
         assign BU291_B[5] = n1069; 
         assign BU291_B[6] = n1070; 
         assign BU291_B[7] = n1071; 
      wire [8 : 0] BU291_Q; 
         assign n1115 = BU291_Q[0]; 
         assign n1116 = BU291_Q[1]; 
         assign n1117 = BU291_Q[2]; 
         assign n1118 = BU291_Q[3]; 
         assign n1119 = BU291_Q[4]; 
         assign n1120 = BU291_Q[5]; 
         assign n1121 = BU291_Q[6]; 
         assign n1122 = BU291_Q[7]; 
         assign n1123 = BU291_Q[8]; 
      wire BU291_CLK; 
         assign BU291_CLK = n133; 
      wire BU291_CE; 
         assign BU291_CE = n134; 
      C_ADDSUB_V7_0 #( 
         0    /* c_add_mode*/, 
         "000000000"    /* c_ainit_val*/, 
         0    /* c_a_type*/, 
         8    /* c_a_width*/, 
         0    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         0    /* c_b_type*/, 
         "000000000"    /* c_b_value*/, 
         8    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         8    /* c_high_bit*/, 
         1    /* c_latency*/, 
         0    /* c_low_bit*/, 
         9    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU291( 
         .A(BU291_A), 
         .B(BU291_B), 
         .Q(BU291_Q), 
         .CLK(BU291_CLK), 
         .CE(BU291_CE) 
      ); 
 
      wire [3 : 0] BU222_I; 
         assign BU222_I[0] = n1023; 
         assign BU222_I[1] = n1024; 
         assign BU222_I[2] = n1025; 
         assign BU222_I[3] = n1021; 
      wire BU222_T; 
         assign BU222_T = 1'b0; 
      wire BU222_EN; 
         assign BU222_EN = 1'b0; 
      wire BU222_Q; 
      wire BU222_CLK; 
         assign BU222_CLK = 1'b0; 
      wire BU222_CE; 
         assign BU222_CE = 1'b0; 
      wire BU222_ACLR; 
         assign BU222_ACLR = 1'b0; 
      wire BU222_ASET; 
         assign BU222_ASET = 1'b0; 
      wire BU222_AINIT; 
         assign BU222_AINIT = 1'b0; 
      wire BU222_SCLR; 
         assign BU222_SCLR = 1'b0; 
      wire BU222_SSET; 
         assign BU222_SSET = 1'b0; 
      wire BU222_SINIT; 
         assign BU222_SINIT = 1'b0; 
      wire BU222_O; 
         assign n1022 = BU222_O; 
      C_GATE_BIT_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         4    /* c_gate_type*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_ce*/, 
         1    /* c_has_o*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         4    /* c_inputs*/, 
         "0000"    /* c_input_inv_mask*/, 
         0    /* c_pipe_stages*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         1    /* c_sync_priority*/ 
      ) 
      BU222( 
         .I(BU222_I), 
         .T(BU222_T), 
         .EN(BU222_EN), 
         .Q(BU222_Q), 
         .CLK(BU222_CLK), 
         .CE(BU222_CE), 
         .ACLR(BU222_ACLR), 
         .ASET(BU222_ASET), 
         .AINIT(BU222_AINIT), 
         .SCLR(BU222_SCLR), 
         .SSET(BU222_SSET), 
         .SINIT(BU222_SINIT), 
         .O(BU222_O) 
      ); 
 
      wire BU227_CLK; 
         assign BU227_CLK = n133; 
      wire BU227_SDIN; 
         assign BU227_SDIN = n1022; 
      wire [12 : 0] BU227_Q; 
         assign n1023 = BU227_Q[0]; 
         assign n1024 = BU227_Q[2]; 
         assign n1025 = BU227_Q[3]; 
         assign n1014 = BU227_Q[5]; 
         assign n1015 = BU227_Q[6]; 
         assign n1016 = BU227_Q[7]; 
         assign n1017 = BU227_Q[8]; 
         assign n1018 = BU227_Q[9]; 
         assign n1019 = BU227_Q[10]; 
         assign n1020 = BU227_Q[11]; 
         assign n1021 = BU227_Q[12]; 
      wire BU227_CE; 
         assign BU227_CE = n134; 
      C_SHIFT_FD_V7_0 #( 
         "1000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         5    /* c_fill_data*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_d*/, 
         0    /* c_has_lsb_2_msb*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         1    /* c_has_sdin*/, 
         0    /* c_has_sdout*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         0    /* c_shift_type*/, 
         "1000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         13    /* c_width*/ 
      ) 
      BU227( 
         .CLK(BU227_CLK), 
         .SDIN(BU227_SDIN), 
         .Q(BU227_Q), 
         .CE(BU227_CE) 
      ); 
 
      wire [3 : 0] BU256_I; 
         assign BU256_I[0] = n1073; 
         assign BU256_I[1] = n1074; 
         assign BU256_I[2] = n1067; 
         assign BU256_I[3] = n1071; 
      wire BU256_T; 
         assign BU256_T = 1'b0; 
      wire BU256_EN; 
         assign BU256_EN = 1'b0; 
      wire BU256_Q; 
      wire BU256_CLK; 
         assign BU256_CLK = 1'b0; 
      wire BU256_CE; 
         assign BU256_CE = 1'b0; 
      wire BU256_ACLR; 
         assign BU256_ACLR = 1'b0; 
      wire BU256_ASET; 
         assign BU256_ASET = 1'b0; 
      wire BU256_AINIT; 
         assign BU256_AINIT = 1'b0; 
      wire BU256_SCLR; 
         assign BU256_SCLR = 1'b0; 
      wire BU256_SSET; 
         assign BU256_SSET = 1'b0; 
      wire BU256_SINIT; 
         assign BU256_SINIT = 1'b0; 
      wire BU256_O; 
         assign n1072 = BU256_O; 
      C_GATE_BIT_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         4    /* c_gate_type*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_ce*/, 
         1    /* c_has_o*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         4    /* c_inputs*/, 
         "0000"    /* c_input_inv_mask*/, 
         0    /* c_pipe_stages*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         1    /* c_sync_priority*/ 
      ) 
      BU256( 
         .I(BU256_I), 
         .T(BU256_T), 
         .EN(BU256_EN), 
         .Q(BU256_Q), 
         .CLK(BU256_CLK), 
         .CE(BU256_CE), 
         .ACLR(BU256_ACLR), 
         .ASET(BU256_ASET), 
         .AINIT(BU256_AINIT), 
         .SCLR(BU256_SCLR), 
         .SSET(BU256_SSET), 
         .SINIT(BU256_SINIT), 
         .O(BU256_O) 
      ); 
 
      wire BU261_CLK; 
         assign BU261_CLK = n133; 
      wire BU261_SDIN; 
         assign BU261_SDIN = n1072; 
      wire [13 : 0] BU261_Q; 
         assign n1073 = BU261_Q[0]; 
         assign n1074 = BU261_Q[5]; 
         assign n1064 = BU261_Q[6]; 
         assign n1065 = BU261_Q[7]; 
         assign n1066 = BU261_Q[8]; 
         assign n1067 = BU261_Q[9]; 
         assign n1068 = BU261_Q[10]; 
         assign n1069 = BU261_Q[11]; 
         assign n1070 = BU261_Q[12]; 
         assign n1071 = BU261_Q[13]; 
      wire BU261_CE; 
         assign BU261_CE = n134; 
      C_SHIFT_FD_V7_0 #( 
         "10000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         5    /* c_fill_data*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_d*/, 
         0    /* c_has_lsb_2_msb*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         1    /* c_has_sdin*/, 
         0    /* c_has_sdout*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         0    /* c_shift_type*/, 
         "10000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         14    /* c_width*/ 
      ) 
      BU261( 
         .CLK(BU261_CLK), 
         .SDIN(BU261_SDIN), 
         .Q(BU261_Q), 
         .CE(BU261_CE) 
      ); 
 
      wire [7 : 0] BU423_A; 
         assign BU423_A[0] = n1124; 
         assign BU423_A[1] = n1125; 
         assign BU423_A[2] = n1126; 
         assign BU423_A[3] = n1127; 
         assign BU423_A[4] = n1128; 
         assign BU423_A[5] = n1129; 
         assign BU423_A[6] = n1130; 
         assign BU423_A[7] = n1131; 
      wire [7 : 0] BU423_B; 
         assign BU423_B[0] = n1170; 
         assign BU423_B[1] = n1171; 
         assign BU423_B[2] = n1172; 
         assign BU423_B[3] = n1173; 
         assign BU423_B[4] = n1174; 
         assign BU423_B[5] = n1175; 
         assign BU423_B[6] = n1176; 
         assign BU423_B[7] = n1177; 
      wire [8 : 0] BU423_Q; 
         assign n1223 = BU423_Q[0]; 
         assign n1224 = BU423_Q[1]; 
         assign n1225 = BU423_Q[2]; 
         assign n1226 = BU423_Q[3]; 
         assign n1227 = BU423_Q[4]; 
         assign n1228 = BU423_Q[5]; 
         assign n1229 = BU423_Q[6]; 
         assign n1230 = BU423_Q[7]; 
         assign n1231 = BU423_Q[8]; 
      wire BU423_CLK; 
         assign BU423_CLK = n133; 
      wire BU423_CE; 
         assign BU423_CE = n134; 
      C_ADDSUB_V7_0 #( 
         0    /* c_add_mode*/, 
         "000000000"    /* c_ainit_val*/, 
         0    /* c_a_type*/, 
         8    /* c_a_width*/, 
         0    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         0    /* c_b_type*/, 
         "000000000"    /* c_b_value*/, 
         8    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         8    /* c_high_bit*/, 
         1    /* c_latency*/, 
         0    /* c_low_bit*/, 
         9    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU423( 
         .A(BU423_A), 
         .B(BU423_B), 
         .Q(BU423_Q), 
         .CLK(BU423_CLK), 
         .CE(BU423_CE) 
      ); 
 
      wire [1 : 0] BU346_I; 
         assign BU346_I[0] = n1133; 
         assign BU346_I[1] = n1131; 
      wire BU346_T; 
         assign BU346_T = 1'b0; 
      wire BU346_EN; 
         assign BU346_EN = 1'b0; 
      wire BU346_Q; 
      wire BU346_CLK; 
         assign BU346_CLK = 1'b0; 
      wire BU346_CE; 
         assign BU346_CE = 1'b0; 
      wire BU346_ACLR; 
         assign BU346_ACLR = 1'b0; 
      wire BU346_ASET; 
         assign BU346_ASET = 1'b0; 
      wire BU346_AINIT; 
         assign BU346_AINIT = 1'b0; 
      wire BU346_SCLR; 
         assign BU346_SCLR = 1'b0; 
      wire BU346_SSET; 
         assign BU346_SSET = 1'b0; 
      wire BU346_SINIT; 
         assign BU346_SINIT = 1'b0; 
      wire BU346_O; 
         assign n1132 = BU346_O; 
      C_GATE_BIT_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         4    /* c_gate_type*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_ce*/, 
         1    /* c_has_o*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         2    /* c_inputs*/, 
         "00"    /* c_input_inv_mask*/, 
         0    /* c_pipe_stages*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         1    /* c_sync_priority*/ 
      ) 
      BU346( 
         .I(BU346_I), 
         .T(BU346_T), 
         .EN(BU346_EN), 
         .Q(BU346_Q), 
         .CLK(BU346_CLK), 
         .CE(BU346_CE), 
         .ACLR(BU346_ACLR), 
         .ASET(BU346_ASET), 
         .AINIT(BU346_AINIT), 
         .SCLR(BU346_SCLR), 
         .SSET(BU346_SSET), 
         .SINIT(BU346_SINIT), 
         .O(BU346_O) 
      ); 
 
      wire BU351_CLK; 
         assign BU351_CLK = n133; 
      wire BU351_SDIN; 
         assign BU351_SDIN = n1132; 
      wire [14 : 0] BU351_Q; 
         assign n1133 = BU351_Q[0]; 
         assign n1124 = BU351_Q[7]; 
         assign n1125 = BU351_Q[8]; 
         assign n1126 = BU351_Q[9]; 
         assign n1127 = BU351_Q[10]; 
         assign n1128 = BU351_Q[11]; 
         assign n1129 = BU351_Q[12]; 
         assign n1130 = BU351_Q[13]; 
         assign n1131 = BU351_Q[14]; 
      wire BU351_CE; 
         assign BU351_CE = n134; 
      C_SHIFT_FD_V7_0 #( 
         "100000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         5    /* c_fill_data*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_d*/, 
         0    /* c_has_lsb_2_msb*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         1    /* c_has_sdin*/, 
         0    /* c_has_sdout*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         0    /* c_shift_type*/, 
         "100000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         15    /* c_width*/ 
      ) 
      BU351( 
         .CLK(BU351_CLK), 
         .SDIN(BU351_SDIN), 
         .Q(BU351_Q), 
         .CE(BU351_CE) 
      ); 
 
      wire [3 : 0] BU384_I; 
         assign BU384_I[0] = n1179; 
         assign BU384_I[1] = n1180; 
         assign BU384_I[2] = n1173; 
         assign BU384_I[3] = n1177; 
      wire BU384_T; 
         assign BU384_T = 1'b0; 
      wire BU384_EN; 
         assign BU384_EN = 1'b0; 
      wire BU384_Q; 
      wire BU384_CLK; 
         assign BU384_CLK = 1'b0; 
      wire BU384_CE; 
         assign BU384_CE = 1'b0; 
      wire BU384_ACLR; 
         assign BU384_ACLR = 1'b0; 
      wire BU384_ASET; 
         assign BU384_ASET = 1'b0; 
      wire BU384_AINIT; 
         assign BU384_AINIT = 1'b0; 
      wire BU384_SCLR; 
         assign BU384_SCLR = 1'b0; 
      wire BU384_SSET; 
         assign BU384_SSET = 1'b0; 
      wire BU384_SINIT; 
         assign BU384_SINIT = 1'b0; 
      wire BU384_O; 
         assign n1178 = BU384_O; 
      C_GATE_BIT_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         4    /* c_gate_type*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_ce*/, 
         1    /* c_has_o*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         4    /* c_inputs*/, 
         "0000"    /* c_input_inv_mask*/, 
         0    /* c_pipe_stages*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         1    /* c_sync_priority*/ 
      ) 
      BU384( 
         .I(BU384_I), 
         .T(BU384_T), 
         .EN(BU384_EN), 
         .Q(BU384_Q), 
         .CLK(BU384_CLK), 
         .CE(BU384_CE), 
         .ACLR(BU384_ACLR), 
         .ASET(BU384_ASET), 
         .AINIT(BU384_AINIT), 
         .SCLR(BU384_SCLR), 
         .SSET(BU384_SSET), 
         .SINIT(BU384_SINIT), 
         .O(BU384_O) 
      ); 
 
      wire BU389_CLK; 
         assign BU389_CLK = n133; 
      wire BU389_SDIN; 
         assign BU389_SDIN = n1178; 
      wire [15 : 0] BU389_Q; 
         assign n1179 = BU389_Q[0]; 
         assign n1180 = BU389_Q[2]; 
         assign n1170 = BU389_Q[8]; 
         assign n1171 = BU389_Q[9]; 
         assign n1172 = BU389_Q[10]; 
         assign n1173 = BU389_Q[11]; 
         assign n1174 = BU389_Q[12]; 
         assign n1175 = BU389_Q[13]; 
         assign n1176 = BU389_Q[14]; 
         assign n1177 = BU389_Q[15]; 
      wire BU389_CE; 
         assign BU389_CE = n134; 
      C_SHIFT_FD_V7_0 #( 
         "1000000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         5    /* c_fill_data*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_d*/, 
         0    /* c_has_lsb_2_msb*/, 
         1    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         1    /* c_has_sdin*/, 
         0    /* c_has_sdout*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         0    /* c_shift_type*/, 
         "1000000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         16    /* c_width*/ 
      ) 
      BU389( 
         .CLK(BU389_CLK), 
         .SDIN(BU389_SDIN), 
         .Q(BU389_Q), 
         .CE(BU389_CE) 
      ); 
 
      wire [13 : 0] BU742_D; 
         assign BU742_D[0] = n45; 
         assign BU742_D[1] = n46; 
         assign BU742_D[2] = n47; 
         assign BU742_D[3] = n48; 
         assign BU742_D[4] = n49; 
         assign BU742_D[5] = n50; 
         assign BU742_D[6] = n51; 
         assign BU742_D[7] = n52; 
         assign BU742_D[8] = n53; 
         assign BU742_D[9] = n54; 
         assign BU742_D[10] = n55; 
         assign BU742_D[11] = n56; 
         assign BU742_D[12] = n57; 
         assign BU742_D[13] = n58; 
      wire [13 : 0] BU742_Q; 
         assign n1867 = BU742_Q[0]; 
         assign n1868 = BU742_Q[1]; 
         assign n1869 = BU742_Q[2]; 
         assign n1870 = BU742_Q[3]; 
         assign n1871 = BU742_Q[4]; 
         assign n1872 = BU742_Q[5]; 
         assign n1873 = BU742_Q[6]; 
         assign n1874 = BU742_Q[7]; 
         assign n1875 = BU742_Q[8]; 
         assign n1876 = BU742_Q[9]; 
         assign n1877 = BU742_Q[10]; 
         assign n1878 = BU742_Q[11]; 
         assign n1879 = BU742_Q[12]; 
         assign n1880 = BU742_Q[13]; 
      wire BU742_CLK; 
         assign BU742_CLK = n133; 
      wire BU742_CE; 
         assign BU742_CE = n134; 
      C_REG_FD_V7_0 #( 
         "00000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "00000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         14    /* c_width*/ 
      ) 
      BU742( 
         .D(BU742_D), 
         .Q(BU742_Q), 
         .CLK(BU742_CLK), 
         .CE(BU742_CE) 
      ); 
 
      wire [11 : 0] BU773_A; 
         assign BU773_A[0] = n1867; 
         assign BU773_A[1] = n1868; 
         assign BU773_A[2] = n1869; 
         assign BU773_A[3] = n1870; 
         assign BU773_A[4] = n1871; 
         assign BU773_A[5] = n1872; 
         assign BU773_A[6] = n1873; 
         assign BU773_A[7] = n1874; 
         assign BU773_A[8] = n1875; 
         assign BU773_A[9] = n1876; 
         assign BU773_A[10] = n1877; 
         assign BU773_A[11] = n1878; 
      wire BU773_BYPASS; 
         assign BU773_BYPASS = n1879; 
      wire BU773_CLK; 
         assign BU773_CLK = n133; 
      wire [12 : 0] BU773_Q; 
         assign n1907 = BU773_Q[0]; 
         assign n1908 = BU773_Q[1]; 
         assign n1909 = BU773_Q[2]; 
         assign n1910 = BU773_Q[3]; 
         assign n1911 = BU773_Q[4]; 
         assign n1912 = BU773_Q[5]; 
         assign n1913 = BU773_Q[6]; 
         assign n1914 = BU773_Q[7]; 
         assign n1915 = BU773_Q[8]; 
         assign n1916 = BU773_Q[9]; 
         assign n1917 = BU773_Q[10]; 
         assign n1918 = BU773_Q[11]; 
      wire BU773_CE; 
         assign BU773_CE = n134; 
      C_TWOS_COMP_V7_0 #( 
         "0000000000000"    /* c_ainit_val*/, 
         1    /* c_bypass_enable*/, 
         1    /* c_bypass_low*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_bypass*/, 
         1    /* c_has_ce*/, 
         1    /* c_has_q*/, 
         0    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         0    /* c_pipe_stages*/, 
         "0000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         12    /* c_width*/ 
      ) 
      BU773( 
         .A(BU773_A), 
         .BYPASS(BU773_BYPASS), 
         .CLK(BU773_CLK), 
         .Q(BU773_Q), 
         .CE(BU773_CE) 
      ); 
 
      wire BU866_CLK; 
         assign BU866_CLK = n133; 
      wire [0 : 0] BU866_D; 
         assign BU866_D[0] = n1880; 
      wire [0 : 0] BU866_Q; 
         assign n1881 = BU866_Q[0]; 
      wire BU866_CE; 
         assign BU866_CE = n134; 
      C_SHIFT_RAM_V7_0 #( 
         1    /* c_addr_width*/, 
         "0"    /* c_ainit_val*/, 
         "0"    /* c_default_data*/, 
         2    /* c_default_data_radix*/, 
         2    /* c_depth*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_generate_mif*/, 
         0    /* c_has_a*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "null"    /* c_mem_init_file*/, 
         2    /* c_mem_init_radix*/, 
         0    /* c_read_mif*/, 
         1    /* c_reg_last_bit*/, 
         0    /* c_shift_type*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         1    /* c_width*/ 
      ) 
      BU866( 
         .CLK(BU866_CLK), 
         .D(BU866_D), 
         .Q(BU866_Q), 
         .CE(BU866_CE) 
      ); 
 
      wire BU874_CLK; 
         assign BU874_CLK = n133; 
      wire [0 : 0] BU874_D; 
         assign BU874_D[0] = n1879; 
      wire [0 : 0] BU874_Q; 
         assign n1882 = BU874_Q[0]; 
      wire BU874_CE; 
         assign BU874_CE = n134; 
      C_SHIFT_RAM_V7_0 #( 
         1    /* c_addr_width*/, 
         "0"    /* c_ainit_val*/, 
         "0"    /* c_default_data*/, 
         2    /* c_default_data_radix*/, 
         2    /* c_depth*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_generate_mif*/, 
         0    /* c_has_a*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "null"    /* c_mem_init_file*/, 
         2    /* c_mem_init_radix*/, 
         0    /* c_read_mif*/, 
         1    /* c_reg_last_bit*/, 
         0    /* c_shift_type*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         1    /* c_width*/ 
      ) 
      BU874( 
         .CLK(BU874_CLK), 
         .D(BU874_D), 
         .Q(BU874_Q), 
         .CE(BU874_CE) 
      ); 
 
      defparam BU885.INIT = 'h9595; 
      wire BU885_I0; 
         assign BU885_I0 = n1881; 
      wire BU885_I1; 
         assign BU885_I1 = n1882; 
      wire BU885_I2; 
         assign BU885_I2 = n1923; 
      wire BU885_I3; 
         assign BU885_I3 = 1'b0; 
      wire BU885_O; 
         assign n2340 = BU885_O; 
      LUT4       BU885( 
         .I0(BU885_I0), 
         .I1(BU885_I1), 
         .I2(BU885_I2), 
         .I3(BU885_I3), 
         .O(BU885_O) 
      ); 
 
      wire BU886_D; 
         assign BU886_D = n2340; 
      wire BU886_C; 
         assign BU886_C = n133; 
      wire BU886_CE; 
         assign BU886_CE = n134; 
      wire BU886_PRE; 
         assign BU886_PRE = 1'b0; 
      wire BU886_Q; 
         assign n1925 = BU886_Q; 
      FDPE       BU886( 
         .D(BU886_D), 
         .C(BU886_C), 
         .CE(BU886_CE), 
         .PRE(BU886_PRE), 
         .Q(BU886_Q) 
      ); 
 
      defparam BU890.INIT = 'h002a; 
      wire BU890_I0; 
         assign BU890_I0 = n1881; 
      wire BU890_I1; 
         assign BU890_I1 = n1882; 
      wire BU890_I2; 
         assign BU890_I2 = n1923; 
      wire BU890_I3; 
         assign BU890_I3 = n1924; 
      wire BU890_O; 
         assign n2359 = BU890_O; 
      LUT4       BU890( 
         .I0(BU890_I0), 
         .I1(BU890_I1), 
         .I2(BU890_I2), 
         .I3(BU890_I3), 
         .O(BU890_O) 
      ); 
 
      wire BU891_D; 
         assign BU891_D = n2359; 
      wire BU891_C; 
         assign BU891_C = n133; 
      wire BU891_CE; 
         assign BU891_CE = n134; 
      wire BU891_Q; 
         assign n1926 = BU891_Q; 
      FDE       BU891( 
         .D(BU891_D), 
         .C(BU891_C), 
         .CE(BU891_CE), 
         .Q(BU891_Q) 
      ); 
 
      defparam BU895.INIT = 'hc0c0; 
      wire BU895_I0; 
         assign BU895_I0 = 1'b0; 
      wire BU895_I1; 
         assign BU895_I1 = n1882; 
      wire BU895_I2; 
         assign BU895_I2 = n1923; 
      wire BU895_I3; 
         assign BU895_I3 = 1'b0; 
      wire BU895_O; 
         assign n2377 = BU895_O; 
      LUT4       BU895( 
         .I0(BU895_I0), 
         .I1(BU895_I1), 
         .I2(BU895_I2), 
         .I3(BU895_I3), 
         .O(BU895_O) 
      ); 
 
      wire BU896_D; 
         assign BU896_D = n2377; 
      wire BU896_C; 
         assign BU896_C = n133; 
      wire BU896_CE; 
         assign BU896_CE = n134; 
      wire BU896_Q; 
         assign n1922 = BU896_Q; 
      FDE       BU896( 
         .D(BU896_D), 
         .C(BU896_C), 
         .CE(BU896_CE), 
         .Q(BU896_Q) 
      ); 
 
      wire [11 : 0] BU898_A; 
         assign BU898_A[0] = n1907; 
         assign BU898_A[1] = n1908; 
         assign BU898_A[2] = n1909; 
         assign BU898_A[3] = n1910; 
         assign BU898_A[4] = n1911; 
         assign BU898_A[5] = n1912; 
         assign BU898_A[6] = n1913; 
         assign BU898_A[7] = n1914; 
         assign BU898_A[8] = n1915; 
         assign BU898_A[9] = n1916; 
         assign BU898_A[10] = n1917; 
         assign BU898_A[11] = n1918; 
      wire BU898_CLK; 
         assign BU898_CLK = n133; 
      wire BU898_CE; 
         assign BU898_CE = n134; 
      wire BU898_ACLR; 
         assign BU898_ACLR = 1'b0; 
      wire BU898_QA_GE_B; 
         assign n1924 = BU898_QA_GE_B; 
      C_COMPARE_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         1    /* c_b_constant*/, 
         "111111110010"    /* c_b_value*/, 
         1    /* c_data_type*/, 
         0    /* c_enable_rlocs*/, 
         1    /* c_has_aclr*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_eq_b*/, 
         0    /* c_has_a_ge_b*/, 
         0    /* c_has_a_gt_b*/, 
         0    /* c_has_a_le_b*/, 
         0    /* c_has_a_lt_b*/, 
         0    /* c_has_a_ne_b*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_qa_eq_b*/, 
         1    /* c_has_qa_ge_b*/, 
         0    /* c_has_qa_gt_b*/, 
         0    /* c_has_qa_le_b*/, 
         0    /* c_has_qa_lt_b*/, 
         0    /* c_has_qa_ne_b*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sset*/, 
         0    /* c_pipe_stages*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         12    /* c_width*/ 
      ) 
      BU898( 
         .A(BU898_A), 
         .CLK(BU898_CLK), 
         .CE(BU898_CE), 
         .ACLR(BU898_ACLR), 
         .QA_GE_B(BU898_QA_GE_B) 
      ); 
 
      wire [11 : 0] BU940_A; 
         assign BU940_A[0] = n1907; 
         assign BU940_A[1] = n1908; 
         assign BU940_A[2] = n1909; 
         assign BU940_A[3] = n1910; 
         assign BU940_A[4] = n1911; 
         assign BU940_A[5] = n1912; 
         assign BU940_A[6] = n1913; 
         assign BU940_A[7] = n1914; 
         assign BU940_A[8] = n1915; 
         assign BU940_A[9] = n1916; 
         assign BU940_A[10] = n1917; 
         assign BU940_A[11] = n1918; 
      wire BU940_CLK; 
         assign BU940_CLK = n133; 
      wire BU940_CE; 
         assign BU940_CE = n134; 
      wire BU940_ACLR; 
         assign BU940_ACLR = 1'b0; 
      wire BU940_QA_EQ_B; 
         assign n1923 = BU940_QA_EQ_B; 
      C_COMPARE_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         1    /* c_b_constant*/, 
         "000000000000"    /* c_b_value*/, 
         1    /* c_data_type*/, 
         0    /* c_enable_rlocs*/, 
         1    /* c_has_aclr*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_eq_b*/, 
         0    /* c_has_a_ge_b*/, 
         0    /* c_has_a_gt_b*/, 
         0    /* c_has_a_le_b*/, 
         0    /* c_has_a_lt_b*/, 
         0    /* c_has_a_ne_b*/, 
         1    /* c_has_ce*/, 
         1    /* c_has_qa_eq_b*/, 
         0    /* c_has_qa_ge_b*/, 
         0    /* c_has_qa_gt_b*/, 
         0    /* c_has_qa_le_b*/, 
         0    /* c_has_qa_lt_b*/, 
         0    /* c_has_qa_ne_b*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sset*/, 
         0    /* c_pipe_stages*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         12    /* c_width*/ 
      ) 
      BU940( 
         .A(BU940_A), 
         .CLK(BU940_CLK), 
         .CE(BU940_CE), 
         .ACLR(BU940_ACLR), 
         .QA_EQ_B(BU940_QA_EQ_B) 
      ); 
 
      wire [13 : 0] BU959_D; 
         assign BU959_D[0] = n45; 
         assign BU959_D[1] = n46; 
         assign BU959_D[2] = n47; 
         assign BU959_D[3] = n48; 
         assign BU959_D[4] = n49; 
         assign BU959_D[5] = n50; 
         assign BU959_D[6] = n51; 
         assign BU959_D[7] = n52; 
         assign BU959_D[8] = n53; 
         assign BU959_D[9] = n54; 
         assign BU959_D[10] = n55; 
         assign BU959_D[11] = n56; 
         assign BU959_D[12] = n57; 
         assign BU959_D[13] = n58; 
      wire [13 : 0] BU959_Q; 
         assign n1958 = BU959_Q[0]; 
         assign n1959 = BU959_Q[1]; 
         assign n1960 = BU959_Q[2]; 
         assign n1961 = BU959_Q[3]; 
         assign n1962 = BU959_Q[4]; 
         assign n1963 = BU959_Q[5]; 
         assign n1964 = BU959_Q[6]; 
         assign n1965 = BU959_Q[7]; 
         assign n1966 = BU959_Q[8]; 
         assign n1967 = BU959_Q[9]; 
         assign n1968 = BU959_Q[10]; 
         assign n1969 = BU959_Q[11]; 
         assign n1970 = BU959_Q[12]; 
         assign n1971 = BU959_Q[13]; 
      wire BU959_CLK; 
         assign BU959_CLK = n133; 
      wire BU959_CE; 
         assign BU959_CE = n134; 
      C_REG_FD_V7_0 #( 
         "00000000000000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "00000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         14    /* c_width*/ 
      ) 
      BU959( 
         .D(BU959_D), 
         .Q(BU959_Q), 
         .CLK(BU959_CLK), 
         .CE(BU959_CE) 
      ); 
 
      wire [11 : 0] BU990_A; 
         assign BU990_A[0] = n1958; 
         assign BU990_A[1] = n1959; 
         assign BU990_A[2] = n1960; 
         assign BU990_A[3] = n1961; 
         assign BU990_A[4] = n1962; 
         assign BU990_A[5] = n1963; 
         assign BU990_A[6] = n1964; 
         assign BU990_A[7] = n1965; 
         assign BU990_A[8] = n1966; 
         assign BU990_A[9] = n1967; 
         assign BU990_A[10] = n1968; 
         assign BU990_A[11] = n1969; 
      wire BU990_BYPASS; 
         assign BU990_BYPASS = n1970; 
      wire BU990_CLK; 
         assign BU990_CLK = n133; 
      wire [12 : 0] BU990_Q; 
         assign n1998 = BU990_Q[0]; 
         assign n1999 = BU990_Q[1]; 
         assign n2000 = BU990_Q[2]; 
         assign n2001 = BU990_Q[3]; 
         assign n2002 = BU990_Q[4]; 
         assign n2003 = BU990_Q[5]; 
         assign n2004 = BU990_Q[6]; 
         assign n2005 = BU990_Q[7]; 
         assign n2006 = BU990_Q[8]; 
         assign n2007 = BU990_Q[9]; 
         assign n2008 = BU990_Q[10]; 
         assign n2009 = BU990_Q[11]; 
      wire BU990_CE; 
         assign BU990_CE = n134; 
      C_TWOS_COMP_V7_0 #( 
         "0000000000000"    /* c_ainit_val*/, 
         1    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_bypass*/, 
         1    /* c_has_ce*/, 
         1    /* c_has_q*/, 
         0    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         0    /* c_pipe_stages*/, 
         "0000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         12    /* c_width*/ 
      ) 
      BU990( 
         .A(BU990_A), 
         .BYPASS(BU990_BYPASS), 
         .CLK(BU990_CLK), 
         .Q(BU990_Q), 
         .CE(BU990_CE) 
      ); 
 
      wire BU1085_CLK; 
         assign BU1085_CLK = n133; 
      wire [0 : 0] BU1085_D; 
         assign BU1085_D[0] = n1971; 
      wire [0 : 0] BU1085_Q; 
         assign n1972 = BU1085_Q[0]; 
      wire BU1085_CE; 
         assign BU1085_CE = n134; 
      C_SHIFT_RAM_V7_0 #( 
         1    /* c_addr_width*/, 
         "0"    /* c_ainit_val*/, 
         "0"    /* c_default_data*/, 
         2    /* c_default_data_radix*/, 
         2    /* c_depth*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_generate_mif*/, 
         0    /* c_has_a*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "null"    /* c_mem_init_file*/, 
         2    /* c_mem_init_radix*/, 
         0    /* c_read_mif*/, 
         1    /* c_reg_last_bit*/, 
         0    /* c_shift_type*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         1    /* c_width*/ 
      ) 
      BU1085( 
         .CLK(BU1085_CLK), 
         .D(BU1085_D), 
         .Q(BU1085_Q), 
         .CE(BU1085_CE) 
      ); 
 
      wire BU1093_CLK; 
         assign BU1093_CLK = n133; 
      wire [0 : 0] BU1093_D; 
         assign BU1093_D[0] = n1970; 
      wire [0 : 0] BU1093_Q; 
         assign n1973 = BU1093_Q[0]; 
      wire BU1093_CE; 
         assign BU1093_CE = n134; 
      C_SHIFT_RAM_V7_0 #( 
         1    /* c_addr_width*/, 
         "0"    /* c_ainit_val*/, 
         "0"    /* c_default_data*/, 
         2    /* c_default_data_radix*/, 
         2    /* c_depth*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_generate_mif*/, 
         0    /* c_has_a*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         "null"    /* c_mem_init_file*/, 
         2    /* c_mem_init_radix*/, 
         0    /* c_read_mif*/, 
         1    /* c_reg_last_bit*/, 
         0    /* c_shift_type*/, 
         "0"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         1    /* c_width*/ 
      ) 
      BU1093( 
         .CLK(BU1093_CLK), 
         .D(BU1093_D), 
         .Q(BU1093_Q), 
         .CE(BU1093_CE) 
      ); 
 
      defparam BU1104.INIT = 'ha9a9; 
      wire BU1104_I0; 
         assign BU1104_I0 = n1972; 
      wire BU1104_I1; 
         assign BU1104_I1 = n1973; 
      wire BU1104_I2; 
         assign BU1104_I2 = n2014; 
      wire BU1104_I3; 
         assign BU1104_I3 = 1'b0; 
      wire BU1104_O; 
         assign n2659 = BU1104_O; 
      LUT4       BU1104( 
         .I0(BU1104_I0), 
         .I1(BU1104_I1), 
         .I2(BU1104_I2), 
         .I3(BU1104_I3), 
         .O(BU1104_O) 
      ); 
 
      wire BU1105_D; 
         assign BU1105_D = n2659; 
      wire BU1105_C; 
         assign BU1105_C = n133; 
      wire BU1105_CE; 
         assign BU1105_CE = n134; 
      wire BU1105_PRE; 
         assign BU1105_PRE = 1'b0; 
      wire BU1105_Q; 
         assign n2016 = BU1105_Q; 
      FDPE       BU1105( 
         .D(BU1105_D), 
         .C(BU1105_C), 
         .CE(BU1105_CE), 
         .PRE(BU1105_PRE), 
         .Q(BU1105_Q) 
      ); 
 
      defparam BU1109.INIT = 'h0046; 
      wire BU1109_I0; 
         assign BU1109_I0 = n1972; 
      wire BU1109_I1; 
         assign BU1109_I1 = n1973; 
      wire BU1109_I2; 
         assign BU1109_I2 = n2014; 
      wire BU1109_I3; 
         assign BU1109_I3 = n2015; 
      wire BU1109_O; 
         assign n2678 = BU1109_O; 
      LUT4       BU1109( 
         .I0(BU1109_I0), 
         .I1(BU1109_I1), 
         .I2(BU1109_I2), 
         .I3(BU1109_I3), 
         .O(BU1109_O) 
      ); 
 
      wire BU1110_D; 
         assign BU1110_D = n2678; 
      wire BU1110_C; 
         assign BU1110_C = n133; 
      wire BU1110_CE; 
         assign BU1110_CE = n134; 
      wire BU1110_Q; 
         assign n2017 = BU1110_Q; 
      FDE       BU1110( 
         .D(BU1110_D), 
         .C(BU1110_C), 
         .CE(BU1110_CE), 
         .Q(BU1110_Q) 
      ); 
 
      defparam BU1114.INIT = 'h3030; 
      wire BU1114_I0; 
         assign BU1114_I0 = 1'b0; 
      wire BU1114_I1; 
         assign BU1114_I1 = n1973; 
      wire BU1114_I2; 
         assign BU1114_I2 = n2014; 
      wire BU1114_I3; 
         assign BU1114_I3 = 1'b0; 
      wire BU1114_O; 
         assign n2696 = BU1114_O; 
      LUT4       BU1114( 
         .I0(BU1114_I0), 
         .I1(BU1114_I1), 
         .I2(BU1114_I2), 
         .I3(BU1114_I3), 
         .O(BU1114_O) 
      ); 
 
      wire BU1115_D; 
         assign BU1115_D = n2696; 
      wire BU1115_C; 
         assign BU1115_C = n133; 
      wire BU1115_CE; 
         assign BU1115_CE = n134; 
      wire BU1115_Q; 
         assign n2013 = BU1115_Q; 
      FDE       BU1115( 
         .D(BU1115_D), 
         .C(BU1115_C), 
         .CE(BU1115_CE), 
         .Q(BU1115_Q) 
      ); 
 
      wire [11 : 0] BU1117_A; 
         assign BU1117_A[0] = n1998; 
         assign BU1117_A[1] = n1999; 
         assign BU1117_A[2] = n2000; 
         assign BU1117_A[3] = n2001; 
         assign BU1117_A[4] = n2002; 
         assign BU1117_A[5] = n2003; 
         assign BU1117_A[6] = n2004; 
         assign BU1117_A[7] = n2005; 
         assign BU1117_A[8] = n2006; 
         assign BU1117_A[9] = n2007; 
         assign BU1117_A[10] = n2008; 
         assign BU1117_A[11] = n2009; 
      wire BU1117_CLK; 
         assign BU1117_CLK = n133; 
      wire BU1117_CE; 
         assign BU1117_CE = n134; 
      wire BU1117_ACLR; 
         assign BU1117_ACLR = 1'b0; 
      wire BU1117_QA_GE_B; 
         assign n2015 = BU1117_QA_GE_B; 
      C_COMPARE_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         1    /* c_b_constant*/, 
         "111111110010"    /* c_b_value*/, 
         1    /* c_data_type*/, 
         0    /* c_enable_rlocs*/, 
         1    /* c_has_aclr*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_eq_b*/, 
         0    /* c_has_a_ge_b*/, 
         0    /* c_has_a_gt_b*/, 
         0    /* c_has_a_le_b*/, 
         0    /* c_has_a_lt_b*/, 
         0    /* c_has_a_ne_b*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_qa_eq_b*/, 
         1    /* c_has_qa_ge_b*/, 
         0    /* c_has_qa_gt_b*/, 
         0    /* c_has_qa_le_b*/, 
         0    /* c_has_qa_lt_b*/, 
         0    /* c_has_qa_ne_b*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sset*/, 
         0    /* c_pipe_stages*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         12    /* c_width*/ 
      ) 
      BU1117( 
         .A(BU1117_A), 
         .CLK(BU1117_CLK), 
         .CE(BU1117_CE), 
         .ACLR(BU1117_ACLR), 
         .QA_GE_B(BU1117_QA_GE_B) 
      ); 
 
      wire [11 : 0] BU1159_A; 
         assign BU1159_A[0] = n1998; 
         assign BU1159_A[1] = n1999; 
         assign BU1159_A[2] = n2000; 
         assign BU1159_A[3] = n2001; 
         assign BU1159_A[4] = n2002; 
         assign BU1159_A[5] = n2003; 
         assign BU1159_A[6] = n2004; 
         assign BU1159_A[7] = n2005; 
         assign BU1159_A[8] = n2006; 
         assign BU1159_A[9] = n2007; 
         assign BU1159_A[10] = n2008; 
         assign BU1159_A[11] = n2009; 
      wire BU1159_CLK; 
         assign BU1159_CLK = n133; 
      wire BU1159_CE; 
         assign BU1159_CE = n134; 
      wire BU1159_ACLR; 
         assign BU1159_ACLR = 1'b0; 
      wire BU1159_QA_EQ_B; 
         assign n2014 = BU1159_QA_EQ_B; 
      C_COMPARE_V7_0 #( 
         "0"    /* c_ainit_val*/, 
         1    /* c_b_constant*/, 
         "000000000000"    /* c_b_value*/, 
         1    /* c_data_type*/, 
         0    /* c_enable_rlocs*/, 
         1    /* c_has_aclr*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_eq_b*/, 
         0    /* c_has_a_ge_b*/, 
         0    /* c_has_a_gt_b*/, 
         0    /* c_has_a_le_b*/, 
         0    /* c_has_a_lt_b*/, 
         0    /* c_has_a_ne_b*/, 
         1    /* c_has_ce*/, 
         1    /* c_has_qa_eq_b*/, 
         0    /* c_has_qa_ge_b*/, 
         0    /* c_has_qa_gt_b*/, 
         0    /* c_has_qa_le_b*/, 
         0    /* c_has_qa_lt_b*/, 
         0    /* c_has_qa_ne_b*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sset*/, 
         0    /* c_pipe_stages*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         12    /* c_width*/ 
      ) 
      BU1159( 
         .A(BU1159_A), 
         .CLK(BU1159_CLK), 
         .CE(BU1159_CE), 
         .ACLR(BU1159_ACLR), 
         .QA_EQ_B(BU1159_QA_EQ_B) 
      ); 
 
      wire [11 : 0] BU652_addra; 
         assign BU652_addra[11] = n1918; 
         assign BU652_addra[10] = n1917; 
         assign BU652_addra[9] = n1916; 
         assign BU652_addra[8] = n1915; 
         assign BU652_addra[7] = n1914; 
         assign BU652_addra[6] = n1913; 
         assign BU652_addra[5] = n1912; 
         assign BU652_addra[4] = n1911; 
         assign BU652_addra[3] = n1910; 
         assign BU652_addra[2] = n1909; 
         assign BU652_addra[1] = n1908; 
         assign BU652_addra[0] = n1907; 
      wire [11 : 0] BU652_addrb; 
         assign BU652_addrb[11] = n2009; 
         assign BU652_addrb[10] = n2008; 
         assign BU652_addrb[9] = n2007; 
         assign BU652_addrb[8] = n2006; 
         assign BU652_addrb[7] = n2005; 
         assign BU652_addrb[6] = n2004; 
         assign BU652_addrb[5] = n2003; 
         assign BU652_addrb[4] = n2002; 
         assign BU652_addrb[3] = n2001; 
         assign BU652_addrb[2] = n2000; 
         assign BU652_addrb[1] = n1999; 
         assign BU652_addrb[0] = n1998; 
      wire BU652_clka; 
         assign BU652_clka = n133; 
      wire BU652_clkb; 
         assign BU652_clkb = n133; 
      wire [14 : 0] BU652_dina; 
         assign BU652_dina[14] = 1'b0; 
         assign BU652_dina[13] = 1'b0; 
         assign BU652_dina[12] = 1'b0; 
         assign BU652_dina[11] = 1'b0; 
         assign BU652_dina[10] = 1'b0; 
         assign BU652_dina[9] = 1'b0; 
         assign BU652_dina[8] = 1'b0; 
         assign BU652_dina[7] = 1'b0; 
         assign BU652_dina[6] = 1'b0; 
         assign BU652_dina[5] = 1'b0; 
         assign BU652_dina[4] = 1'b0; 
         assign BU652_dina[3] = 1'b0; 
         assign BU652_dina[2] = 1'b0; 
         assign BU652_dina[1] = 1'b0; 
         assign BU652_dina[0] = 1'b0; 
      wire [14 : 0] BU652_dinb; 
         assign BU652_dinb[14] = 1'b0; 
         assign BU652_dinb[13] = 1'b0; 
         assign BU652_dinb[12] = 1'b0; 
         assign BU652_dinb[11] = 1'b0; 
         assign BU652_dinb[10] = 1'b0; 
         assign BU652_dinb[9] = 1'b0; 
         assign BU652_dinb[8] = 1'b0; 
         assign BU652_dinb[7] = 1'b0; 
         assign BU652_dinb[6] = 1'b0; 
         assign BU652_dinb[5] = 1'b0; 
         assign BU652_dinb[4] = 1'b0; 
         assign BU652_dinb[3] = 1'b0; 
         assign BU652_dinb[2] = 1'b0; 
         assign BU652_dinb[1] = 1'b0; 
         assign BU652_dinb[0] = 1'b0; 
      wire [14 : 0] BU652_douta; 
         assign n1941 = BU652_douta[14]; 
         assign n1940 = BU652_douta[13]; 
         assign n1939 = BU652_douta[12]; 
         assign n1938 = BU652_douta[11]; 
         assign n1937 = BU652_douta[10]; 
         assign n1936 = BU652_douta[9]; 
         assign n1935 = BU652_douta[8]; 
         assign n1934 = BU652_douta[7]; 
         assign n1933 = BU652_douta[6]; 
         assign n1932 = BU652_douta[5]; 
         assign n1931 = BU652_douta[4]; 
         assign n1930 = BU652_douta[3]; 
         assign n1929 = BU652_douta[2]; 
         assign n1928 = BU652_douta[1]; 
         assign n1927 = BU652_douta[0]; 
      wire [14 : 0] BU652_doutb; 
         assign n2032 = BU652_doutb[14]; 
         assign n2031 = BU652_doutb[13]; 
         assign n2030 = BU652_doutb[12]; 
         assign n2029 = BU652_doutb[11]; 
         assign n2028 = BU652_doutb[10]; 
         assign n2027 = BU652_doutb[9]; 
         assign n2026 = BU652_doutb[8]; 
         assign n2025 = BU652_doutb[7]; 
         assign n2024 = BU652_doutb[6]; 
         assign n2023 = BU652_doutb[5]; 
         assign n2022 = BU652_doutb[4]; 
         assign n2021 = BU652_doutb[3]; 
         assign n2020 = BU652_doutb[2]; 
         assign n2019 = BU652_doutb[1]; 
         assign n2018 = BU652_doutb[0]; 
      wire BU652_ena; 
         assign BU652_ena = n134; 
      wire BU652_enb; 
         assign BU652_enb = n134; 
      wire BU652_nda; 
         assign BU652_nda = 1'b0; 
      wire BU652_ndb; 
         assign BU652_ndb = 1'b0; 
      wire BU652_rfda; 
      wire BU652_rfdb; 
      wire BU652_rdya; 
      wire BU652_rdyb; 
      wire BU652_sinita; 
         assign BU652_sinita = 1'b0; 
      wire BU652_sinitb; 
         assign BU652_sinitb = 1'b0; 
      wire BU652_wea; 
         assign BU652_wea = 1'b0; 
      wire BU652_web; 
         assign BU652_web = 1'b0; 
      BLKMEMDP_V6_0 #( 
         12    /* c_addra_width*/, 
         12    /* c_addrb_width*/, 
         "0000"    /* c_default_data*/, 
         4096    /* c_depth_a*/, 
         4096    /* c_depth_b*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_default_data*/, 
         0    /* c_has_dina*/, 
         0    /* c_has_dinb*/, 
         1    /* c_has_douta*/, 
         1    /* c_has_doutb*/, 
         1    /* c_has_ena*/, 
         1    /* c_has_enb*/, 
         0    /* c_has_limit_data_pitch*/, 
         0    /* c_has_nda*/, 
         0    /* c_has_ndb*/, 
         0    /* c_has_rdya*/, 
         0    /* c_has_rdyb*/, 
         0    /* c_has_rfda*/, 
         0    /* c_has_rfdb*/, 
         0    /* c_has_sinita*/, 
         0    /* c_has_sinitb*/, 
         0    /* c_has_wea*/, 
         0    /* c_has_web*/, 
         18    /* c_limit_data_pitch*/, 
         "ddsqam_SINCOS_TABLE_TRIG_ROM.mif"    /* c_mem_init_file*/, 
         1    /* c_pipe_stages_a*/, 
         1    /* c_pipe_stages_b*/, 
         0    /* c_reg_inputsa*/, 
         0    /* c_reg_inputsb*/, 
         "0000"    /* c_sinita_value*/, 
         "0000"    /* c_sinitb_value*/, 
         15    /* c_width_a*/, 
         15    /* c_width_b*/, 
         0    /* c_write_modea*/, 
         0    /* c_write_modeb*/, 
         "0"    /* c_ybottom_addr*/, 
         1    /* c_yclka_is_rising*/, 
         1    /* c_yclkb_is_rising*/, 
         1    /* c_yena_is_high*/, 
         1    /* c_yenb_is_high*/, 
         "hierarchy1"    /* c_yhierarchy*/, 
         0    /* c_ymake_bmm*/, 
         "4kx4"    /* c_yprimitive_type*/, 
         1    /* c_ysinita_is_high*/, 
         1    /* c_ysinitb_is_high*/, 
         "1024"    /* c_ytop_addr*/, 
         0    /* c_yuse_single_primitive*/, 
         1    /* c_ywea_is_high*/, 
         1    /* c_yweb_is_high*/, 
         1    /* c_yydisable_warnings*/ 
      ) 
      BU652( 
         .ADDRA(BU652_addra), 
         .ADDRB(BU652_addrb), 
         .CLKA(BU652_clka), 
         .CLKB(BU652_clkb), 
         .DINA(BU652_dina), 
         .DINB(BU652_dinb), 
         .DOUTA(BU652_douta), 
         .DOUTB(BU652_doutb), 
         .ENA(BU652_ena), 
         .ENB(BU652_enb), 
         .NDA(BU652_nda), 
         .NDB(BU652_ndb), 
         .RFDA(BU652_rfda), 
         .RFDB(BU652_rfdb), 
         .RDYA(BU652_rdya), 
         .RDYB(BU652_rdyb), 
         .SINITA(BU652_sinita), 
         .SINITB(BU652_sinitb), 
         .WEA(BU652_wea), 
         .WEB(BU652_web) 
      ); 
 
      wire [15 : 0] BU1178_A; 
         assign BU1178_A[0] = 1'b0; 
         assign BU1178_A[1] = 1'b0; 
         assign BU1178_A[2] = 1'b0; 
         assign BU1178_A[3] = 1'b0; 
         assign BU1178_A[4] = 1'b0; 
         assign BU1178_A[5] = 1'b0; 
         assign BU1178_A[6] = 1'b0; 
         assign BU1178_A[7] = 1'b0; 
         assign BU1178_A[8] = 1'b0; 
         assign BU1178_A[9] = 1'b0; 
         assign BU1178_A[10] = 1'b0; 
         assign BU1178_A[11] = 1'b0; 
         assign BU1178_A[12] = 1'b0; 
         assign BU1178_A[13] = 1'b0; 
         assign BU1178_A[14] = 1'b0; 
         assign BU1178_A[15] = 1'b0; 
      wire [15 : 0] BU1178_B; 
         assign BU1178_B[0] = n1927; 
         assign BU1178_B[1] = n1928; 
         assign BU1178_B[2] = n1929; 
         assign BU1178_B[3] = n1930; 
         assign BU1178_B[4] = n1931; 
         assign BU1178_B[5] = n1932; 
         assign BU1178_B[6] = n1933; 
         assign BU1178_B[7] = n1934; 
         assign BU1178_B[8] = n1935; 
         assign BU1178_B[9] = n1936; 
         assign BU1178_B[10] = n1937; 
         assign BU1178_B[11] = n1938; 
         assign BU1178_B[12] = n1939; 
         assign BU1178_B[13] = n1940; 
         assign BU1178_B[14] = n1941; 
         assign BU1178_B[15] = n1922; 
      wire BU1178_C_IN; 
         assign BU1178_C_IN = n1926; 
      wire BU1178_ADD; 
         assign BU1178_ADD = n1925; 
      wire [15 : 0] BU1178_Q; 
         assign n135 = BU1178_Q[0]; 
         assign n136 = BU1178_Q[1]; 
         assign n137 = BU1178_Q[2]; 
         assign n138 = BU1178_Q[3]; 
         assign n139 = BU1178_Q[4]; 
         assign n140 = BU1178_Q[5]; 
         assign n141 = BU1178_Q[6]; 
         assign n142 = BU1178_Q[7]; 
         assign n143 = BU1178_Q[8]; 
         assign n144 = BU1178_Q[9]; 
         assign n145 = BU1178_Q[10]; 
         assign n146 = BU1178_Q[11]; 
         assign n147 = BU1178_Q[12]; 
         assign n148 = BU1178_Q[13]; 
         assign n149 = BU1178_Q[14]; 
         assign n150 = BU1178_Q[15]; 
      wire BU1178_CLK; 
         assign BU1178_CLK = n133; 
      wire BU1178_CE; 
         assign BU1178_CE = n2049; 
      C_ADDSUB_V7_0 #( 
         2    /* c_add_mode*/, 
         "0000000000000000"    /* c_ainit_val*/, 
         1    /* c_a_type*/, 
         16    /* c_a_width*/, 
         1    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         1    /* c_b_type*/, 
         "0000000000000000"    /* c_b_value*/, 
         16    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         1    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         1    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         15    /* c_high_bit*/, 
         1    /* c_latency*/, 
         0    /* c_low_bit*/, 
         16    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "0000000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU1178( 
         .A(BU1178_A), 
         .B(BU1178_B), 
         .C_IN(BU1178_C_IN), 
         .ADD(BU1178_ADD), 
         .Q(BU1178_Q), 
         .CLK(BU1178_CLK), 
         .CE(BU1178_CE) 
      ); 
 
      wire BU1275_CLK; 
         assign BU1275_CLK = n133; 
      wire BU1275_SDIN; 
         assign BU1275_SDIN = n44; 
      wire BU1275_SDOUT; 
         assign n2067 = BU1275_SDOUT; 
      wire BU1275_CE; 
         assign BU1275_CE = n134; 
      C_SHIFT_FD_V7_0 #( 
         "0000"    /* c_ainit_val*/, 
         0    /* c_enable_rlocs*/, 
         5    /* c_fill_data*/, 
         0    /* c_has_aclr*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         1    /* c_has_ce*/, 
         0    /* c_has_d*/, 
         0    /* c_has_lsb_2_msb*/, 
         0    /* c_has_q*/, 
         0    /* c_has_sclr*/, 
         1    /* c_has_sdin*/, 
         1    /* c_has_sdout*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         1    /* c_shift_type*/, 
         "0000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/, 
         4    /* c_width*/ 
      ) 
      BU1275( 
         .CLK(BU1275_CLK), 
         .SDIN(BU1275_SDIN), 
         .SDOUT(BU1275_SDOUT), 
         .CE(BU1275_CE) 
      ); 
 
      defparam BU1287.INIT = 'h8888; 
      wire BU1287_I0; 
         assign BU1287_I0 = n134; 
      wire BU1287_I1; 
         assign BU1287_I1 = n2067; 
      wire BU1287_I2; 
         assign BU1287_I2 = 1'b0; 
      wire BU1287_I3; 
         assign BU1287_I3 = 1'b0; 
      wire BU1287_O; 
         assign n2049 = BU1287_O; 
      LUT4       BU1287( 
         .I0(BU1287_I0), 
         .I1(BU1287_I1), 
         .I2(BU1287_I2), 
         .I3(BU1287_I3), 
         .O(BU1287_O) 
      ); 
 
      wire [15 : 0] BU1290_A; 
         assign BU1290_A[0] = 1'b0; 
         assign BU1290_A[1] = 1'b0; 
         assign BU1290_A[2] = 1'b0; 
         assign BU1290_A[3] = 1'b0; 
         assign BU1290_A[4] = 1'b0; 
         assign BU1290_A[5] = 1'b0; 
         assign BU1290_A[6] = 1'b0; 
         assign BU1290_A[7] = 1'b0; 
         assign BU1290_A[8] = 1'b0; 
         assign BU1290_A[9] = 1'b0; 
         assign BU1290_A[10] = 1'b0; 
         assign BU1290_A[11] = 1'b0; 
         assign BU1290_A[12] = 1'b0; 
         assign BU1290_A[13] = 1'b0; 
         assign BU1290_A[14] = 1'b0; 
         assign BU1290_A[15] = 1'b0; 
      wire [15 : 0] BU1290_B; 
         assign BU1290_B[0] = n2018; 
         assign BU1290_B[1] = n2019; 
         assign BU1290_B[2] = n2020; 
         assign BU1290_B[3] = n2021; 
         assign BU1290_B[4] = n2022; 
         assign BU1290_B[5] = n2023; 
         assign BU1290_B[6] = n2024; 
         assign BU1290_B[7] = n2025; 
         assign BU1290_B[8] = n2026; 
         assign BU1290_B[9] = n2027; 
         assign BU1290_B[10] = n2028; 
         assign BU1290_B[11] = n2029; 
         assign BU1290_B[12] = n2030; 
         assign BU1290_B[13] = n2031; 
         assign BU1290_B[14] = n2032; 
         assign BU1290_B[15] = n2013; 
      wire BU1290_C_IN; 
         assign BU1290_C_IN = n2017; 
      wire BU1290_ADD; 
         assign BU1290_ADD = n2016; 
      wire [15 : 0] BU1290_Q; 
         assign n151 = BU1290_Q[0]; 
         assign n152 = BU1290_Q[1]; 
         assign n153 = BU1290_Q[2]; 
         assign n154 = BU1290_Q[3]; 
         assign n155 = BU1290_Q[4]; 
         assign n156 = BU1290_Q[5]; 
         assign n157 = BU1290_Q[6]; 
         assign n158 = BU1290_Q[7]; 
         assign n159 = BU1290_Q[8]; 
         assign n160 = BU1290_Q[9]; 
         assign n161 = BU1290_Q[10]; 
         assign n162 = BU1290_Q[11]; 
         assign n163 = BU1290_Q[12]; 
         assign n164 = BU1290_Q[13]; 
         assign n165 = BU1290_Q[14]; 
         assign n166 = BU1290_Q[15]; 
      wire BU1290_CLK; 
         assign BU1290_CLK = n133; 
      wire BU1290_CE; 
         assign BU1290_CE = n2049; 
      C_ADDSUB_V7_0 #( 
         2    /* c_add_mode*/, 
         "0000000000000000"    /* c_ainit_val*/, 
         1    /* c_a_type*/, 
         16    /* c_a_width*/, 
         1    /* c_bypass_enable*/, 
         0    /* c_bypass_low*/, 
         0    /* c_b_constant*/, 
         1    /* c_b_type*/, 
         "0000000000000000"    /* c_b_value*/, 
         16    /* c_b_width*/, 
         0    /* c_enable_rlocs*/, 
         0    /* c_has_aclr*/, 
         1    /* c_has_add*/, 
         0    /* c_has_ainit*/, 
         0    /* c_has_aset*/, 
         0    /* c_has_a_signed*/, 
         0    /* c_has_bypass*/, 
         0    /* c_has_bypass_with_cin*/, 
         0    /* c_has_b_in*/, 
         0    /* c_has_b_out*/, 
         0    /* c_has_b_signed*/, 
         1    /* c_has_ce*/, 
         1    /* c_has_c_in*/, 
         0    /* c_has_c_out*/, 
         0    /* c_has_ovfl*/, 
         1    /* c_has_q*/, 
         0    /* c_has_q_b_out*/, 
         0    /* c_has_q_c_out*/, 
         0    /* c_has_q_ovfl*/, 
         1    /* c_has_s*/, 
         0    /* c_has_sclr*/, 
         0    /* c_has_sinit*/, 
         0    /* c_has_sset*/, 
         15    /* c_high_bit*/, 
         1    /* c_latency*/, 
         0    /* c_low_bit*/, 
         16    /* c_out_width*/, 
         0    /* c_pipe_stages*/, 
         "0000000000000000"    /* c_sinit_val*/, 
         0    /* c_sync_enable*/, 
         0    /* c_sync_priority*/ 
      ) 
      BU1290( 
         .A(BU1290_A), 
         .B(BU1290_B), 
         .C_IN(BU1290_C_IN), 
         .ADD(BU1290_ADD), 
         .Q(BU1290_Q), 
         .CLK(BU1290_CLK), 
         .CE(BU1290_CE) 
      ); 
 
//synthesis translate_on 
 
endmodule