www.pudn.com > nandflash_1G08U0A.rar > drv_nandfls.h
////////////////////////////////////////////////////////////////////////
// 文件名 ：drv_nandfls.c
// 文件功能 ：系统读取Nand Flash驱动
// 作者 ：xyliu
// 创建时间 ：2003年5月09日
// 处理器 : Epson E0C33S01
// 项目名称 ：
// 备注 ：适合硬件板卡Epson S1C33 Star、Legend MobilePhone
// 可以驱动的Nand Flash型号：
// K9F1208U0 2003/05/09
// K9F5616 2003/05/09
//
////////////////////////////////////////////////////////////////////////
// 历史记录：
// 编号 日期 作者 备注
// 1 2004/10/20 xyliu 加入了K9F1208U0M支持
////////////////////////////////////////////////////////////////////////
#ifndef _Nand_Fls_H
//Use K9F1208U0M
typedef struct _tag_nand_fls
{
unsigned char maker_code;
unsigned char device_code;
unsigned char rev1;
unsigned char mutiplane_code;
}t_nand_fls_id;
#define MAKER_CODE 0xEC
//#define DEVICE_CODE 0x76
//#define MULTI_PLANE_CODE 0xC0
#define DEVICE_CODE 0xF1
#define MULTI_PLANE_CODE 0x15
#define Nand_Fls_Status_Reg 0x402DD //Port3 data register
#define NAND_FLS_READY 1
#define NAND_FLS_BUSY 0
/*Flash command */
#define READ_MODE1_CMD 0x0000
#define READ_ADV_CMD 0x0030
#define READ_MODE2_CMD 0x0001
#define READ_MODE3_CMD 0x0050
#define AUTO_WRITE_CMD 0x0080
#define PAGE_WRITE_CMD 0x0010
#define READ_STATUS_CMD 0x0070
#define AUTO_ERASE_CMD 0x0060
#define ERASE_CMD 0x00D0
#define RESET_CMD 0x00ff
#define READ_ID 0x0090
#define READ_ID_ADDR 0x0000
//flash device information const
#define TOTAL_SIZE 0x1000000
#define MAX_BLK_NUM 1024 // mcp
#define MAX_PG_NUM 0x20 //32
#define PG_SIZE 0x200
#define BLK_SIZE 0x4000
#define NAND_Flash_BASE_ADDRESS 0x4000000 //both flash and SMC map to area 15
#define FLASH_SUCCESS 0x0
#define FLASH_FAILED 0x1
#define FLASH_PAR_ERR 0x2
#define FLASH_DATA_ERR 0x4
#define FLASH_TIME_OUT_ERR 0x5
#define FLASH_WRITE_ERR 0x6
#define FLASH_ERASE_ERR 0x7
#define FLASH_ECC_ERROR 0x8
#define FLASH_ID_ERROR 0x9
//---------------------------------------------------------------------------------
// macro definition
//---------------------------------------------------------------------------------
/* control port register */
#define SET_ALE_OUTPUT *(volatile unsigned char*)0x402da|=0x20 //p25
#define SET_CLE_OUTPUT *(volatile unsigned char*)0x402da|=0x10 //p24
#define SET_ALE_H *(volatile unsigned char*)0x402d9|=0x20 //set p25 H
#define SET_ALE_L *(volatile unsigned char*)0x402d9&=0xdf //set p25 L
#define SET_CLE_H *(volatile unsigned char*)0x402d9|=0x10 //set p24 H
#define SET_CLE_L *(volatile unsigned char*)0x402d9&=0xef //set p24 L
#define SET_WP_OUTPUT *(volatile unsigned char*)0x300021|=0x01 // set P40 output
#define SET_WP_H *(volatile unsigned char*)0x300020|=0x01 // set P40 high
#define SET_WP_L *(volatile unsigned char*)0x300020&=0xfe // set P40 low
#define SET_WP_GPIO *(volatile unsigned char*)0x300048|=0x01 // set P40 as GPIO, not A25
#define SET_BUSY_INPUT *(volatile unsigned char*)0x300f47&=0xdf // set PD5 input
#define CHECK_BUSY (*(volatile unsigned char*)0x300f46 & 0x20 ) // PD5=L mean busy
//Dual address DMA setting (ch2)
#define DMA_DUAL *(volatile unsigned short*)0x48242 = 0x8000 // dual address mode
#define DMA_EN *(volatile unsigned char*)0x4824c |= 0x01 // enable Ch.2 DMA
#define DMA_TRIG *(volatile unsigned char*)0x4029a |= 0x04 // software trigger Ch.2 DMA
#define CHECK_DMA_END (*(volatile unsigned char*)0x4824c & 0x01 )
// ECC setting
#define EN_ECC *(volatile unsigned char*)0x300102|=0x01 // enable ecc check
#define DIS_ECC *(volatile unsigned char*)0x300102 &=0xfe // disable ecc check
#define SET_DEVICE_16 *(volatile unsigned char*)0x300103|=0x01 // 16 bit device
#define SET_DEVICE_8 *(volatile unsigned char*)0x300103&=0xfe // 8 bit device
#define RESET_ECC *(volatile unsigned char*)0x300101|=0x01 // reset ECC
#define CHECK_ECC_READY (*(volatile unsigned char*)0x300101& 0x1) // if can start ecc check
#define ECC_AREA0_COL_ADDR (unsigned char*)0x300104
/* nand flash only control port register */
#define SET_NAND_CE_OUTPUT *(volatile unsigned char*)0x300023|=0x02 //set P51 output
#define SET_NAND_CE_H *(volatile unsigned char*)0x300022|=0x2 //set CE H
#define SET_NAND_CE_L *(volatile unsigned char*)0x300022&=0xfd //set CE L
#define SET_NAND_CE_CE *(volatile unsigned char*)0x30004a &=0xf3 // set p51 as CE15&16 for CE don't-care flash
#define SET_NAND_CE_GPIO *(volatile unsigned char*)0x30004a |=0x4 // set p51 as GPIO
/*smt only control port register*/
#define SET_SMC_CE_OUTPUT *(volatile unsigned char*)0x300023|=0x10 //set P54 output
#define SET_SMC_CE_H *(volatile unsigned char*)0x300022|=0x10 //set CE H
#define SET_SMC_CE_L *(volatile unsigned char*)0x300022&=0xef //set CE L
#define SET_SMC_CE_GPIO *(volatile unsigned char*)0x30004b |=0x01 // set p54 as GPIO
#define CLR_SMIFREG *(volatile unsigned char*)0x300047&=0xf0 // clear smart media i/f lower 4 bit
#define SET_SMIF_WE *(volatile unsigned char*)0x300047|=0x01 // set p34 as SMWE
#define SET_SMIF_RD *(volatile unsigned char*)0x300047|=0x04 // set p35 as SMRD
#define SET_NAND_AREA *(volatile unsigned char*)0x300100=0x0 // not select boot mode , area 15; both SMC, flash all map to area 15
//flash all map to area 15
//Nand Flash Command and Data Port address
#define Nand_Fls_Data_ADD 0x4000000
#define Nand_Fls_COMM_ADD 0x4000004
#define Nand_Fls_Reg_ADD 0x4000008
#define Nand_Fls_ADD_ADD 0x4000008
//#define Nand_Fls_Data_ADD 0x1000000
//#define Nand_Fls_COMM_ADD 0x1000004
//#define Nand_Fls_Reg_ADD 0x1000008
//#define Nand_Fls_ADD_ADD 0x1000008
#define BLOCK_Er_SETUP_COMMAND 0x60 //Auto Block Erase Setup Command
#define Er_COMMAND 0xD0 //Erase Command
#define READ_St_COMMAND 0x70 //Read Status Command
#define SEQ_DATA_IN_COMMAND 0x80 //Sequential Data Input Command
#define PROG_COMMAND 0x10 //Program Command
//#define NFS_MAX_PLANE 4
#define NFS_MAX_BLOCK 1024//4096
#define NFS_MAX_PAGE 64//131072//65536//32768//16384//131072
//Operation Nand Flash Status Flag
#define ERASE_OK 0 //Erase OK
#define ERASE_ERROR 1 //Erase Error
#define ERASE_OK_FLAG 0
#define ERASE_ERROR_FLAG 1
#define NAND_INIT_OK 0
#define NAND_INIT_ERROR 1
#define PROG_OK 0 //Program OK
#define PROG_ERROR 1 //Program Error
#define PROG_OK_FLAG 0 //Program OK
#define PROG_ERROR_FLAG 1 //Program Error
//#define NAND_FLS_MAIN 512
//#define NAND_FLS_ALL 528
#define NAND_FLS_MAIN 2048
#define NAND_FLS_ALL 2112
//#define SET_NAND_CE_HIGH REG_CHAR(IO_P2D_ADDR) |= 0x04
#define SET_NAND_CE_HIGH REG_CHAR(0x300022) |= 0x02;
//#define SET_NAND_CE_LOW REG_CHAR(IO_P2D_ADDR) &= 0xfb
#define SET_NAND_CE_LOW REG_CHAR(0x300022) &= 0xfd;
int nand_fls_init(void);
int nand_fls_write_page(unsigned char *data,unsigned int page_num,unsigned int block_num);
int nand_fls_read_page(unsigned char *data,unsigned int page_num,unsigned int block_num);
int nand_fls_erase_block(unsigned int Block_Number);
void Test_Nand_Flash(void);
void nand_fls_tst_all(void);
#endif